So that we can use write-protection for code later.
It is REPOST.
It includes suggestion from "Kinney, Michael D" <michael.d.kin...@intel.com>
For IA32 assembly, can we combine into a single OR
instruction that sets both page enable and WP?
For X64, does it make sense to use single OR instruction
instead of 2 BTS instructions as well?
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen....@intel.com>
Suggested-by: "Kinney, Michael D" <michael.d.kin...@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kin...@intel.com>
Cc: "Fan, Jeff" <jeff....@intel.com>
Cc: "Kinney, Michael D" <michael.d.kin...@intel.com>
Cc: "Laszlo Ersek" <ler...@redhat.com>
Cc: "Paolo Bonzini" <pbonz...@redhat.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 2 +-
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 2 +-
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 2 +-
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
index fbaa072..ec5b9a0 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
@@ -123,7 +123,7 @@ L11:
L12: # as cr4.PGE is not set here,
refresh cr3
movl %eax, %cr4 # in PreModifyMtrrs() to flush TLB.
movl %cr0, %ebx
- orl $0x080000000, %ebx # enable paging
+ orl $0x080010000, %ebx # enable paging + WP
movl %ebx, %cr0
leal DSC_OFFSET(%edi),%ebx
movw DSC_DS(%ebx),%ax
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
index 8a12927..ac1a9b4 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
@@ -129,7 +129,7 @@ gSmiCr3 DD ?
@@: ; as cr4.PGE is not set here, refresh
cr3
mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
mov ebx, cr0
- or ebx, 080000000h ; enable paging
+ or ebx, 080010000h ; enable paging + WP
mov cr0, ebx
lea ebx, [edi + DSC_OFFSET]
mov ax, [ebx + DSC_DS]
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
index b488b74..7e9ac58 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
@@ -144,7 +144,7 @@ Base:
orb $1,%ah
wrmsr
movq %cr0, %rbx
- btsl $31, %ebx
+ orl $0x080010000, %ebx # enable paging + WP
movq %rbx, %cr0
retf
LongMode: # long mode (64-bit code) starts here
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
index 4f5c03c..094cf2c 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
@@ -140,7 +140,7 @@ Base:
or ah, 1
wrmsr
mov rbx, cr0
- bts ebx, 31
+ or ebx, 080010000h ; enable paging + WP
mov cr0, rbx
retf
@LongMode: ; long mode (64-bit code) starts here
--
1.9.5.msysgit.0
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