The RVCT compiler may emit calls to the various __aeabi_c?cmp??
functions, which return their results via the CPU condition flags
C and Z. According to ARM doc IHI 0043D 'Run-time ABI for the ARM
architecture':

    The 3-way comparison functions c*cmple, c*cmpeq and c*rcmple return
    their results in the CPSR Z and C flags. C is clear only if the operands
    are ordered and the first operand is less than the second. Z is set only
    when the operands are ordered and equal.

Add implementations for the double and float variants of the above.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <[email protected]>
---
 ArmPkg/Library/ArmSoftFloatLib/Arm/__aeabi_cdcmp.asm | 54 ++++++++++++++++++++
 ArmPkg/Library/ArmSoftFloatLib/Arm/__aeabi_cfcmp.asm | 50 ++++++++++++++++++
 ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf   |  3 ++
 3 files changed, 107 insertions(+)

diff --git a/ArmPkg/Library/ArmSoftFloatLib/Arm/__aeabi_cdcmp.asm 
b/ArmPkg/Library/ArmSoftFloatLib/Arm/__aeabi_cdcmp.asm
new file mode 100644
index 000000000000..1cc5b83d0cf6
--- /dev/null
+++ b/ArmPkg/Library/ArmSoftFloatLib/Arm/__aeabi_cdcmp.asm
@@ -0,0 +1,54 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2015, Linaro Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD 
License
+// which accompanies this distribution.  The full text of the license may be 
found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+    EXPORT      __aeabi_cdrcmple
+    EXPORT      __aeabi_cdcmpeq
+    EXPORT      __aeabi_cdcmple
+    IMPORT      float64_eq
+    IMPORT      float64_lt
+
+    AREA        __aeabi_cdcmp, CODE, READONLY
+
+CPSR_C_BIT      EQU   (1 << 29)
+CPSR_Z_BIT      EQU   (1 << 30)
+
+__aeabi_cdrcmple
+    MOV         IP, R0
+    MOV         R0, R2
+    MOV         R2, IP
+
+    MOV         IP, R1
+    MOV         R1, R3
+    MOV         R3, IP
+
+__aeabi_cdcmpeq
+__aeabi_cdcmple
+    PUSH        {LR}
+    PUSH        {R0 - R3}
+    BL          float64_eq
+    TEQ         R0, #0
+    BEQ         NotEqual
+    MSR         CPSR_f, #CPSR_C_BIT :OR: CPSR_Z_BIT
+    ADD         SP, SP, #0x10
+    POP         {PC}
+
+NotEqual
+    POP         {R0 - R3}
+    BL          float64_lt
+    TEQ         R0, #0
+    MSREQ       CPSR_f, #CPSR_C_BIT
+    MSRNE       CPSR_f, #0
+    POP         {PC}
+
+    END
diff --git a/ArmPkg/Library/ArmSoftFloatLib/Arm/__aeabi_cfcmp.asm 
b/ArmPkg/Library/ArmSoftFloatLib/Arm/__aeabi_cfcmp.asm
new file mode 100644
index 000000000000..f50b91de15a1
--- /dev/null
+++ b/ArmPkg/Library/ArmSoftFloatLib/Arm/__aeabi_cfcmp.asm
@@ -0,0 +1,50 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2015, Linaro Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD 
License
+// which accompanies this distribution.  The full text of the license may be 
found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+    EXPORT      __aeabi_cfrcmple
+    EXPORT      __aeabi_cfcmpeq
+    EXPORT      __aeabi_cfcmple
+    IMPORT      float32_eq
+    IMPORT      float32_lt
+
+    AREA        __aeabi_cfcmp, CODE, READONLY
+
+CPSR_C_BIT      EQU   (1 << 29)
+CPSR_Z_BIT      EQU   (1 << 30)
+
+__aeabi_cfrcmple
+    MOV         IP, R0
+    MOV         R0, R1
+    MOV         R1, IP
+
+__aeabi_cfcmpeq
+__aeabi_cfcmple
+    PUSH        {LR}
+    PUSH        {R0 - R1}
+    BL          float32_eq
+    TEQ         R0, #0
+    BEQ         NotEqual
+    MSR         CPSR_f, #CPSR_C_BIT :OR: CPSR_Z_BIT
+    ADD         SP, SP, #0x8
+    POP         {PC}
+
+NotEqual
+    POP         {R0 - R1}
+    BL          float32_lt
+    TEQ         R0, #0
+    MSREQ       CPSR_f, #CPSR_C_BIT
+    MSRNE       CPSR_f, #0
+    POP         {PC}
+
+    END
diff --git a/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf 
b/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf
index 39c74bf1a3c2..3d3445197f49 100644
--- a/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf
+++ b/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.inf
@@ -41,6 +41,9 @@ [Sources]
   Arm/__aeabi_dcmpun.c
   Arm/__aeabi_fcmpun.c
 
+  Arm/__aeabi_cdcmp.asm   | RVCT
+  Arm/__aeabi_cfcmp.asm   | RVCT
+
 [Packages]
   MdePkg/MdePkg.dec
 
-- 
1.9.1

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