C99 does not define left-shifting negative values, so make all [positive] preprocessor constants unsigned explicitly, so they do not become negative values after bitwise negation.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <[email protected]> --- PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c | 44 ++++++++++---------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c b/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c index 5698e935b01f..6ed761544a8a 100644 --- a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c +++ b/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c @@ -19,32 +19,32 @@ //--------------------------------------------- // UART Register Offsets //--------------------------------------------- -#define BAUD_LOW_OFFSET 0x00 -#define BAUD_HIGH_OFFSET 0x01 -#define IER_OFFSET 0x01 -#define LCR_SHADOW_OFFSET 0x01 -#define FCR_SHADOW_OFFSET 0x02 -#define IR_CONTROL_OFFSET 0x02 -#define FCR_OFFSET 0x02 -#define EIR_OFFSET 0x02 -#define BSR_OFFSET 0x03 -#define LCR_OFFSET 0x03 -#define MCR_OFFSET 0x04 -#define LSR_OFFSET 0x05 -#define MSR_OFFSET 0x06 +#define BAUD_LOW_OFFSET 0x00U +#define BAUD_HIGH_OFFSET 0x01U +#define IER_OFFSET 0x01U +#define LCR_SHADOW_OFFSET 0x01U +#define FCR_SHADOW_OFFSET 0x02U +#define IR_CONTROL_OFFSET 0x02U +#define FCR_OFFSET 0x02U +#define EIR_OFFSET 0x02U +#define BSR_OFFSET 0x03U +#define LCR_OFFSET 0x03U +#define MCR_OFFSET 0x04U +#define LSR_OFFSET 0x05U +#define MSR_OFFSET 0x06U //--------------------------------------------- // UART Register Bit Defines //--------------------------------------------- -#define LSR_TXRDY 0x20 -#define LSR_RXDA 0x01 -#define DLAB 0x01 -#define MCR_DTRC 0x01 -#define MCR_RTS 0x02 -#define MSR_CTS 0x10 -#define MSR_DSR 0x20 -#define MSR_RI 0x40 -#define MSR_DCD 0x80 +#define LSR_TXRDY 0x20U +#define LSR_RXDA 0x01U +#define DLAB 0x01U +#define MCR_DTRC 0x01U +#define MCR_RTS 0x02U +#define MSR_CTS 0x10U +#define MSR_DSR 0x20U +#define MSR_RI 0x40U +#define MSR_DCD 0x80U //--------------------------------------------- // UART Settings -- 2.5.0 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
