From: Evan Lloyd <[email protected]>
Some updates to SCR can cause a problem which manifests as an undefined opcode
exception.
This may be when a speculative secure instruction fetch happens after the NS
bit is set.
An isb is required to make the register change take effect fully.
Contributed-under: Tianocore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <Evan.Lloyd <at> arm.com>
Reviewed-by: Sami Mujawar <Sami.Mujawar <at> arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel <at> linaro.org>
(See http://article.gmane.org/gmane.comp.bios.edk2.devel/1675
never appeared to get merged)
Code at:
https://github.com/EvanLloyd/tianocore/commit/903827785a576fd346475c69c42e5d0aa0c6676c
diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
index 28db98b..50faef4 100644
--- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
@@ -184,6 +184,7 @@ ASM_PFX(ArmWriteCptr):
ASM_PFX(ArmWriteScr):
msr scr_el3, x0 // Secure configuration register EL3
+ isb
ret
ASM_PFX(ArmWriteMVBar):
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
index 59f9918..085f08b 100644
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
@@ -147,6 +147,7 @@ ASM_PFX(ArmReadScr):
ASM_PFX(ArmWriteScr):
mcr p15, 0, r0, c1, c1, 0
+ isb
bx lr
ASM_PFX(ArmReadHVBar):
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
index bdd862a..228d7c8 100644
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
+++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
@@ -121,6 +121,7 @@
RVCT_ASM_EXPORT ArmWriteScr
mcr p15, 0, r0, c1, c1, 0
+ isb
bx lr
RVCT_ASM_EXPORT ArmReadHVBar
--
2.7.0
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