If XD is supported, then SMM enables it. The non-SMM execution
environment can choose to enable or disable XD, so the state of
XD must be detected in each SMI and be enabled/restored.
Cc: Jeff Fan <jeff....@intel.com>
Cc: Jiewen Yao <jiewen....@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kin...@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 18 +++++++++++++++---
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h | 3 ++-
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 79b7c90..185cb3d 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -1,7 +1,7 @@
/** @file
SMM MP service implementation
-Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -1019,6 +1019,7 @@ SmiRendezvous (
BOOLEAN BspInProgress;
UINTN Index;
UINTN Cr2;
+ BOOLEAN XdDisableFlag;
//
// Save Cr2 because Page Fault exception in SMM may override its value
@@ -1078,9 +1079,14 @@ SmiRendezvous (
}
//
- // Try to enable NX
+ // Try to enable XD
//
+ XdDisableFlag = FALSE;
if (mXdSupported) {
+ if ((AsmReadMsr64 (MSR_IA32_MISC_ENABLE) & B_XD_DISABLE_BIT) != 0) {
+ XdDisableFlag = TRUE;
+ AsmMsrAnd64 (MSR_IA32_MISC_ENABLE, ~B_XD_DISABLE_BIT);
+ }
ActivateXd ();
}
@@ -1152,7 +1158,6 @@ SmiRendezvous (
// BSP Handler is always called with a ValidSmi == TRUE
//
BSPHandler (CpuIndex, mSmmMpSyncData->EffectiveSyncMode);
-
} else {
APHandler (CpuIndex, ValidSmi, mSmmMpSyncData->EffectiveSyncMode);
}
@@ -1165,6 +1170,13 @@ SmiRendezvous (
//
while (mSmmMpSyncData->AllCpusInSync) {
CpuPause ();
+ }
+
+ //
+ // Restore XD
+ //
+ if (XdDisableFlag) {
+ AsmMsrOr64 (MSR_IA32_MISC_ENABLE, B_XD_DISABLE_BIT);
}
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
index 4548467..f91c104 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
@@ -1,7 +1,7 @@
/** @file
SMM profile header file.
-Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD
License
which accompanies this distribution. The full text of the license may be
found at
@@ -21,6 +21,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
EXPRESS OR IMPLIED.
/// MSR Register Index
///
#define MSR_IA32_MISC_ENABLE 0x1A0
+#define B_XD_DISABLE_BIT BIT34
//
// External functions
--
2.6.3.windows.1
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