On 03/05/16 10:54, Ni, Ruiyu wrote:
> Laszlo,
>
> Does [0|3|0] contain option rom? (video controller?)
>
> If it contains option rom, PciBusDxe driver has a logic to
>
> convert the PMem64 to PMem32. PMem32 is converted
>
> to Mem32 because COMBINE_MEM_PMEM is set.
>
>
>
> The detailed logic is in PciResourceSupport.c: DegradeResource().
Right; I had found that function before I sent my email, but it looked
quite complex; so I thought I would ask my question without cluttering
the email with doubts about that function.
You are correct: the device is a physical GTX750 GPU assigned to the
guest, and it does have an option ROM.
I saw the comment in the source:
//
// If any child device has both option ROM and 64-bit BAR, degrade its
// PMEM64/MEM64 requests in case that if a legacy option ROM image can
// not access 64-bit resources.
//
but I thought that this degradation would only happen if the option ROM
in question were *for certain* a legacy option ROM *only*. In this case
the GPU has a well-working 64-bit UEFI firmware, so I mostly ignored the
code under the comment.
Now I'm noticing that the condition is:
Temp = PCI_IO_DEVICE_FROM_LINK (ChildDeviceLink);
if (Temp->RomSize != 0) {
i.e., any kind of option ROM suffices to degrade the region.
So, my question is answered. Thank you!
Laszlo
>
>
>
> Regards,
>
> Ray
>
>
>
> *From:*Laszlo Ersek [mailto:ler...@redhat.com]
> *Sent:* Saturday, March 5, 2016 5:41 AM
> *To:* Ni, Ruiyu <ruiyu...@intel.com>
> *Cc:* edk2-devel-ml01 <edk2-de...@ml01.01.org>
> *Subject:* allocation of PMem64 BARs
>
>
>
> Hi Ray,
>
> on top of my pending series
>
> [edk2] [PATCH 0/5] OvmfPkg: enable PCIe on Q35
> http://thread.gmane.org/gmane.comp.bios.edk2.devel/8707
>
> I also have some patches (not posted yet) that enable 64-bit MMIO. I
> tested it and it seems to work, but something is strange to me.
>
> Namely, there is enough room in the non-prefetchable 64-bit aperture for
> allocating some PMem64 BARs (and EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is
> passed to the driver), but the driver decides to allocate those from the
> (also non-prefetchable) 32-bit aperture instead.
>
> It doesn't seem invalid, of course, but I thought that the driver would
> conserve the 32-bit aperture, and allocate everything possible from the
> 64-bit aperture.
>
> I also have a Mem64 BAR, and that gets allocated high just fine.
>
> Here's the initial output from the host bridge driver:
>
>> RootBridge: PciRoot(0x0)
>> Support/Attr: 70069 / 70069
>> DmaAbove4G: No
>> NoExtConfSpace: No
>> AllocAttr: 3 (CombineMemPMem Mem64Decode)
>> Bus: 0 - FF
>> Io: C000 - FFFF
>> Mem: C0000000 - FBFFFFFF
>> MemAbove4G: 180000000 - 97FFFFFFF
>> PMem: 0 - 0
>> PMemAbove4G: 0 - 0
>> PciHostBridgeDxe: IntersectMemoryDescriptor: add [180000000, 980000000):
>> Success
>
> Then the output from the PCI bus driver, interspersed with messages from
> the host bridge driver:
>
>> PCI Bus First Scanning
>> PciBus: Discovered PCI @ [00|00|00]
>>
>> PciBus: Discovered PCI @ [00|01|00]
>> BAR[0]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000;
>> Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000;
>> Offset = 0x14
>> BAR[2]: Type = Mem32; Alignment = 0x1FFF; Length = 0x2000; Offset =
>> 0x18
>> BAR[3]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x1C
>>
>> PciBus: Discovered PCI @ [00|02|00]
>> BAR[0]: Type = Mem64; Alignment = 0x3FFF; Length = 0x4000; Offset =
>> 0x10
>>
>> PciBus: Discovered PCI @ [00|03|00]
>> BAR[0]: Type = Mem32; Alignment = 0xFFFFFF; Length = 0x1000000; Offset
>> = 0x10
>> BAR[1]: Type = PMem64; Alignment = 0xFFFFFFF; Length = 0x10000000;
>> Offset = 0x14
>> BAR[2]: Type = PMem64; Alignment = 0x1FFFFFF; Length = 0x2000000;
>> Offset = 0x1C
>> BAR[3]: Type = Io32; Alignment = 0x7F; Length = 0x80; Offset = 0x24
>>
>> PciBus: Discovered PCI @ [00|04|00]
>> BAR[0]: Type = Mem32; Alignment = 0x3FFF; Length = 0x4000; Offset =
>> 0x10
>>
>> PciBus: Discovered PPB @ [00|1E|00]
>>
>> PciBus: Discovered PPB @ [01|01|00]
>> BAR[0]: Type = Mem64; Alignment = 0xFFF; Length = 0x100; Offset = 0x10
>>
>> PciBus: Discovered PCI @ [02|01|00]
>> BAR[0]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>>
>> PciBus: Discovered PCI @ [02|02|00]
>> BAR[4]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x20
>>
>> PciBus: Discovered PCI @ [02|02|01]
>> BAR[4]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x20
>>
>> PciBus: Discovered PCI @ [02|02|02]
>> BAR[4]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x20
>>
>> PciBus: Discovered PCI @ [02|02|07]
>> BAR[0]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x10
>>
>> PciBus: Discovered PCI @ [02|03|00]
>> BAR[0]: Type = Io32; Alignment = 0x3F; Length = 0x40; Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>>
>> PciBus: Discovered PCI @ [02|04|00]
>> BAR[0]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x10
>>
>> PciBus: Discovered PCI @ [02|05|00]
>> BAR[0]: Type = Io32; Alignment = 0x3F; Length = 0x40; Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>>
>> PciBus: Discovered PCI @ [02|06|00]
>> BAR[0]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>>
>> PciBus: Discovered PCI @ [00|1F|00]
>>
>> PciBus: Discovered PCI @ [00|1F|02]
>> BAR[4]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x20
>> BAR[5]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x24
>>
>> PciBus: Discovered PCI @ [00|1F|03]
>> BAR[4]: Type = Io32; Alignment = 0x3F; Length = 0x40; Offset = 0x20
>>
>> PciBus: Discovered PCI @ [00|00|00]
>>
>> PciBus: Discovered PCI @ [00|01|00]
>> BAR[0]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000;
>> Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0x3FFFFFF; Length = 0x4000000;
>> Offset = 0x14
>> BAR[2]: Type = Mem32; Alignment = 0x1FFF; Length = 0x2000; Offset =
>> 0x18
>> BAR[3]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x1C
>>
>> PciBus: Discovered PCI @ [00|02|00]
>> BAR[0]: Type = Mem64; Alignment = 0x3FFF; Length = 0x4000; Offset =
>> 0x10
>>
>> PciBus: Discovered PCI @ [00|03|00]
>> BAR[0]: Type = Mem32; Alignment = 0xFFFFFF; Length = 0x1000000; Offset
>> = 0x10
>> BAR[1]: Type = PMem64; Alignment = 0xFFFFFFF; Length = 0x10000000;
>> Offset = 0x14
>> BAR[2]: Type = PMem64; Alignment = 0x1FFFFFF; Length = 0x2000000;
>> Offset = 0x1C
>> BAR[3]: Type = Io32; Alignment = 0x7F; Length = 0x80; Offset = 0x24
>>
>> PciBus: Discovered PCI @ [00|04|00]
>> BAR[0]: Type = Mem32; Alignment = 0x3FFF; Length = 0x4000; Offset =
>> 0x10
>>
>> PciBus: Discovered PPB @ [00|1E|00]
>>
>> PciBus: Discovered PPB @ [01|01|00]
>> BAR[0]: Type = Mem64; Alignment = 0xFFF; Length = 0x100; Offset = 0x10
>>
>> PciBus: Discovered PCI @ [02|01|00]
>> BAR[0]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>>
>> PciBus: Discovered PCI @ [02|02|00]
>> BAR[4]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x20
>>
>> PciBus: Discovered PCI @ [02|02|01]
>> BAR[4]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x20
>>
>> PciBus: Discovered PCI @ [02|02|02]
>> BAR[4]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x20
>>
>> PciBus: Discovered PCI @ [02|02|07]
>> BAR[0]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x10
>>
>> PciBus: Discovered PCI @ [02|03|00]
>> BAR[0]: Type = Io32; Alignment = 0x3F; Length = 0x40; Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>>
>> PciBus: Discovered PCI @ [02|04|00]
>> BAR[0]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x10
>>
>> PciBus: Discovered PCI @ [02|05|00]
>> BAR[0]: Type = Io32; Alignment = 0x3F; Length = 0x40; Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>>
>> PciBus: Discovered PCI @ [02|06|00]
>> BAR[0]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x10
>> BAR[1]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x14
>>
>> PciBus: Discovered PCI @ [00|1F|00]
>>
>> PciBus: Discovered PCI @ [00|1F|02]
>> BAR[4]: Type = Io32; Alignment = 0x1F; Length = 0x20; Offset = 0x20
>> BAR[5]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x24
>>
>> PciBus: Discovered PCI @ [00|1F|03]
>> BAR[4]: Type = Io32; Alignment = 0x3F; Length = 0x40; Offset = 0x20
>>
>> PciHostBridge: SubmitResources for PciRoot(0x0)
>> I/O: Granularity/SpecificFlag = 0 / 01
>> Length/Alignment = 0x2000 / 0xFFF
>> Mem: Granularity/SpecificFlag = 32 / 00
>> Length/Alignment = 0x1B300000 / 0xFFFFFFF
>> Mem: Granularity/SpecificFlag = 64 / 00
>> Length/Alignment = 0x100000 / 0xFFFFF
>> PciBus: HostBridge->SubmitResources() - Success
>> PciHostBridge: NotifyPhase (AllocateResources)
>> RootBridge: PciRoot(0x0)
>> Mem: Base/Length/Alignment = C0000000/1B300000/FFFFFFF - Success
>> Mem64: Base/Length/Alignment = 180000000/100000/FFFFF - Success
>> I/O: Base/Length/Alignment = C000/2000/FFF - Success
>> PciBus: HostBridge->NotifyPhase(AllocateResources) - Success
>> PciBus: Resource Map for Root Bridge PciRoot(0x0)
>> Type = Io16; Base = 0xC000; Length = 0x2000; Alignment = 0xFFF
>> Base = 0xC000; Length = 0x1000; Alignment = 0xFFF; Owner = PPB
>> [00|1E|00:**]
>> Base = 0xD000; Length = 0x80; Alignment = 0x7F; Owner = PCI
>> [00|03|00:24]
>> Base = 0xD080; Length = 0x40; Alignment = 0x3F; Owner = PCI
>> [00|1F|03:20]
>> Base = 0xD0C0; Length = 0x20; Alignment = 0x1F; Owner = PCI
>> [00|1F|02:20]
>> Base = 0xD0E0; Length = 0x20; Alignment = 0x1F; Owner = PCI
>> [00|01|00:1C]
>> Type = Mem32; Base = 0xC0000000; Length = 0x1B300000; Alignment =
>> 0xFFFFFFF
>> Base = 0xC0000000; Length = 0x10000000; Alignment = 0xFFFFFFF; Owner =
>> PCI [00|03|00:14]; Type = PMem64
>> Base = 0xD0000000; Length = 0x4000000; Alignment = 0x3FFFFFF; Owner =
>> PCI [00|01|00:14]
>> Base = 0xD4000000; Length = 0x4000000; Alignment = 0x3FFFFFF; Owner =
>> PCI [00|01|00:10]
>> Base = 0xD8000000; Length = 0x2000000; Alignment = 0x1FFFFFF; Owner =
>> PCI [00|03|00:1C]; Type = PMem64
>> Base = 0xDA000000; Length = 0x1000000; Alignment = 0xFFFFFF; Owner =
>> PCI [00|03|00:10]
>> Base = 0xDB000000; Length = 0x200000; Alignment = 0xFFFFF; Owner = PPB
>> [00|1E|00:**]
>> Base = 0xDB200000; Length = 0x4000; Alignment = 0x3FFF; Owner = PCI
>> [00|04|00:10]
>> Base = 0xDB204000; Length = 0x2000; Alignment = 0x1FFF; Owner = PCI
>> [00|01|00:18]
>> Base = 0xDB206000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI
>> [00|1F|02:24]
>> Type = Mem64; Base = 0x180000000; Length = 0x100000; Alignment = 0xFFFFF
>> Base = 0x180000000; Length = 0x4000; Alignment = 0x3FFF; Owner = PCI
>> [00|02|00:10]
>>
>> PciBus: Resource Map for Bridge [00|1E|00]
>> Type = Io16; Base = 0xC000; Length = 0x1000; Alignment = 0xFFF
>> Base = 0xC000; Length = 0x1000; Alignment = 0xFFF; Owner = PPB
>> [01|01|00:**]
>> Type = Mem32; Base = 0xDB000000; Length = 0x200000; Alignment = 0xFFFFF
>> Base = 0xDB000000; Length = 0x100000; Alignment = 0xFFFFF; Owner = PPB
>> [01|01|00:**]
>> Base = 0xDB100000; Length = 0x100; Alignment = 0xFFF; Owner = PPB
>> [01|01|00:10]
>>
>> PciBus: Resource Map for Bridge [01|01|00]
>> Type = Io16; Base = 0xC000; Length = 0x1000; Alignment = 0xFFF
>> Base = 0xC000; Length = 0x40; Alignment = 0x3F; Owner = PCI
>> [02|05|00:10]
>> Base = 0xC040; Length = 0x40; Alignment = 0x3F; Owner = PCI
>> [02|03|00:10]
>> Base = 0xC080; Length = 0x20; Alignment = 0x1F; Owner = PCI
>> [02|06|00:10]
>> Base = 0xC0A0; Length = 0x20; Alignment = 0x1F; Owner = PCI
>> [02|04|00:10]
>> Base = 0xC0C0; Length = 0x20; Alignment = 0x1F; Owner = PCI
>> [02|02|02:20]
>> Base = 0xC0E0; Length = 0x20; Alignment = 0x1F; Owner = PCI
>> [02|02|01:20]
>> Base = 0xC100; Length = 0x20; Alignment = 0x1F; Owner = PCI
>> [02|02|00:20]
>> Base = 0xC120; Length = 0x20; Alignment = 0x1F; Owner = PCI
>> [02|01|00:10]
>> Type = Mem32; Base = 0xDB000000; Length = 0x100000; Alignment = 0xFFFFF
>> Base = 0xDB000000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI
>> [02|06|00:14]
>> Base = 0xDB001000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI
>> [02|05|00:14]
>> Base = 0xDB002000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI
>> [02|03|00:14]
>> Base = 0xDB003000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI
>> [02|02|07:10]
>> Base = 0xDB004000; Length = 0x1000; Alignment = 0xFFF; Owner = PCI
>> [02|01|00:14]
>> Type = Mem32; Base = 0xDB100000; Length = 0x100; Alignment = 0xFFF
>
> As you can see, the [00|03|00] device has two PMem64 BARs (256MB and
> 32MB in size, respectively), but ultimately they are allocated from the
> Mem32 aperture. Why is that?
>
> Whereas device [00|02|00] has a Mem64 BAR (only 16KB in size), which is
> allocated from the Mem64 aperture.
>
> Thanks
> Laszlo
>
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
