Regarding the subject, how about "PATCH v3" rather than "Patch V3"?
Reviewed-by: Jordan Justen <[email protected]> Pushed as db27e9f3d8f007bf26bcb8907ecab5b5f1fb8f24. On 2016-03-15 01:10:40, Ruiyu Ni wrote: > Current implementation only supports legacy region of 440 chip. > When QEMU is launched in Q35 mode using CSM enabled OVMF image, > LegacyBios driver fails to start due to the legacy region > [0xC0000, 0xFFFFF] cannot be written. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ruiyu Ni <[email protected]> > Cc: Justen Jordan <[email protected]> > Cc: Laszlo Ersek <[email protected]> > --- > OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c | 100 > +++++++++++++++++++++---------- > OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h | 26 +++++--- > 2 files changed, 87 insertions(+), 39 deletions(-) > > diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c > b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c > index 44d340b..b929db0 100644 > --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c > +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c > @@ -1,7 +1,7 @@ > /** @file > Legacy Region Support > > - Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR> > + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR> > > This program and the accompanying materials are > licensed and made available under the terms and conditions of the BSD > License > @@ -16,23 +16,24 @@ > #include "LegacyRegion.h" > > // > -// 440 PAM map. > +// 440/Q35 PAM map. > // > -// PAM Range Offset Bits Operation > -// =============== ====== ==== > =============================================================== > -// 0xC0000-0xC3FFF 0x5a 1:0 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xC4000-0xC7FFF 0x5a 5:4 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xC8000-0xCBFFF 0x5b 1:0 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xCC000-0xCFFFF 0x5b 5:4 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xD0000-0xD3FFF 0x5c 1:0 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xD4000-0xD7FFF 0x5c 5:4 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xD8000-0xDBFFF 0x5d 1:0 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xDC000-0xDFFFF 0x5d 5:4 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xE0000-0xE3FFF 0x5e 1:0 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xE4000-0xE7FFF 0x5e 5:4 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xE8000-0xEBFFF 0x5f 1:0 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xEC000-0xEFFFF 0x5f 5:4 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > -// 0xF0000-0xFFFFF 0x59 5:4 00 = DRAM Disabled, 01= Read Only, 10 = > Write Only, 11 = Normal > +// PAM Range Offset Bits Operation > +// 440 Q35 > +// =============== ==== ==== ==== > =============================================================== > +// 0xC0000-0xC3FFF 0x5a 0x91 1:0 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xC4000-0xC7FFF 0x5a 0x91 5:4 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xC8000-0xCBFFF 0x5b 0x92 1:0 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xCC000-0xCFFFF 0x5b 0x92 5:4 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xD0000-0xD3FFF 0x5c 0x93 1:0 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xD4000-0xD7FFF 0x5c 0x93 5:4 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xD8000-0xDBFFF 0x5d 0x94 1:0 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xDC000-0xDFFFF 0x5d 0x94 5:4 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xE0000-0xE3FFF 0x5e 0x95 1:0 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xE4000-0xE7FFF 0x5e 0x95 5:4 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xE8000-0xEBFFF 0x5f 0x96 1:0 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xEC000-0xEFFFF 0x5f 0x96 5:4 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > +// 0xF0000-0xFFFFF 0x59 0x90 5:4 00 = DRAM Disabled, 01= Read Only, 10 > = Write Only, 11 = Normal > // > STATIC LEGACY_MEMORY_SECTION_INFO mSectionArray[] = { > {0xC0000, SIZE_16KB, FALSE, FALSE}, > @@ -50,22 +51,40 @@ STATIC LEGACY_MEMORY_SECTION_INFO mSectionArray[] = { > {0xF0000, SIZE_64KB, FALSE, FALSE} > }; > > -STATIC PAM_REGISTER_VALUE mRegisterValues[] = { > - {REG_PAM1_OFFSET, 0x01, 0x02}, > - {REG_PAM1_OFFSET, 0x10, 0x20}, > - {REG_PAM2_OFFSET, 0x01, 0x02}, > - {REG_PAM2_OFFSET, 0x10, 0x20}, > - {REG_PAM3_OFFSET, 0x01, 0x02}, > - {REG_PAM3_OFFSET, 0x10, 0x20}, > - {REG_PAM4_OFFSET, 0x01, 0x02}, > - {REG_PAM4_OFFSET, 0x10, 0x20}, > - {REG_PAM5_OFFSET, 0x01, 0x02}, > - {REG_PAM5_OFFSET, 0x10, 0x20}, > - {REG_PAM6_OFFSET, 0x01, 0x02}, > - {REG_PAM6_OFFSET, 0x10, 0x20}, > - {REG_PAM0_OFFSET, 0x10, 0x20} > +STATIC PAM_REGISTER_VALUE mRegisterValues440[] = { > + {REG_PAM1_OFFSET_440, 0x01, 0x02}, > + {REG_PAM1_OFFSET_440, 0x10, 0x20}, > + {REG_PAM2_OFFSET_440, 0x01, 0x02}, > + {REG_PAM2_OFFSET_440, 0x10, 0x20}, > + {REG_PAM3_OFFSET_440, 0x01, 0x02}, > + {REG_PAM3_OFFSET_440, 0x10, 0x20}, > + {REG_PAM4_OFFSET_440, 0x01, 0x02}, > + {REG_PAM4_OFFSET_440, 0x10, 0x20}, > + {REG_PAM5_OFFSET_440, 0x01, 0x02}, > + {REG_PAM5_OFFSET_440, 0x10, 0x20}, > + {REG_PAM6_OFFSET_440, 0x01, 0x02}, > + {REG_PAM6_OFFSET_440, 0x10, 0x20}, > + {REG_PAM0_OFFSET_440, 0x10, 0x20} > }; > > +STATIC PAM_REGISTER_VALUE mRegisterValuesQ35[] = { > + {REG_PAM1_OFFSET_Q35, 0x01, 0x02}, > + {REG_PAM1_OFFSET_Q35, 0x10, 0x20}, > + {REG_PAM2_OFFSET_Q35, 0x01, 0x02}, > + {REG_PAM2_OFFSET_Q35, 0x10, 0x20}, > + {REG_PAM3_OFFSET_Q35, 0x01, 0x02}, > + {REG_PAM3_OFFSET_Q35, 0x10, 0x20}, > + {REG_PAM4_OFFSET_Q35, 0x01, 0x02}, > + {REG_PAM4_OFFSET_Q35, 0x10, 0x20}, > + {REG_PAM5_OFFSET_Q35, 0x01, 0x02}, > + {REG_PAM5_OFFSET_Q35, 0x10, 0x20}, > + {REG_PAM6_OFFSET_Q35, 0x01, 0x02}, > + {REG_PAM6_OFFSET_Q35, 0x10, 0x20}, > + {REG_PAM0_OFFSET_Q35, 0x10, 0x20} > +}; > + > +STATIC PAM_REGISTER_VALUE *mRegisterValues; > + > // > // Handle used to install the Legacy Region Protocol > // > @@ -450,6 +469,25 @@ LegacyRegionInit ( > ) > { > EFI_STATUS Status; > + UINT16 HostBridgeDevId; > + > + // > + // Query Host Bridge DID to determine platform type > + // > + HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId); > + switch (HostBridgeDevId) { > + case INTEL_82441_DEVICE_ID: > + mRegisterValues = mRegisterValues440; > + break; > + case INTEL_Q35_MCH_DEVICE_ID: > + mRegisterValues = mRegisterValuesQ35; > + break; > + default: > + DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", > + __FUNCTION__, HostBridgeDevId)); > + ASSERT (FALSE); > + return RETURN_UNSUPPORTED; > + } > > // > // Install the Legacy Region Protocol on a new handle > diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h > b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h > index 805df86..f755a2a 100644 > --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h > +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h > @@ -1,7 +1,7 @@ > /** @file > Legacy Region Support > > - Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR> > + Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR> > > This program and the accompanying materials are > licensed and made available under the terms and conditions of the BSD > License > @@ -21,6 +21,8 @@ > #include <Protocol/LegacyRegion2.h> > > #include <IndustryStandard/Pci.h> > +#include <IndustryStandard/Q35MchIch9.h> > +#include <IndustryStandard/I440FxPiix4.h> > > #include <Library/PciLib.h> > #include <Library/PcdLib.h> > @@ -32,13 +34,21 @@ > #define PAM_PCI_DEV 0 > #define PAM_PCI_FUNC 0 > > -#define REG_PAM0_OFFSET 0x59 // Programmable Attribute Map 0 > -#define REG_PAM1_OFFSET 0x5a // Programmable Attribute Map 1 > -#define REG_PAM2_OFFSET 0x5b // Programmable Attribute Map 2 > -#define REG_PAM3_OFFSET 0x5c // Programmable Attribute Map 3 > -#define REG_PAM4_OFFSET 0x5d // Programmable Attribute Map 4 > -#define REG_PAM5_OFFSET 0x5e // Programmable Attribute Map 5 > -#define REG_PAM6_OFFSET 0x5f // Programmable Attribute Map 6 > +#define REG_PAM0_OFFSET_440 0x59 // Programmable Attribute Map 0 > +#define REG_PAM1_OFFSET_440 0x5a // Programmable Attribute Map 1 > +#define REG_PAM2_OFFSET_440 0x5b // Programmable Attribute Map 2 > +#define REG_PAM3_OFFSET_440 0x5c // Programmable Attribute Map 3 > +#define REG_PAM4_OFFSET_440 0x5d // Programmable Attribute Map 4 > +#define REG_PAM5_OFFSET_440 0x5e // Programmable Attribute Map 5 > +#define REG_PAM6_OFFSET_440 0x5f // Programmable Attribute Map 6 > + > +#define REG_PAM0_OFFSET_Q35 0x90 // Programmable Attribute Map 0 > +#define REG_PAM1_OFFSET_Q35 0x91 // Programmable Attribute Map 1 > +#define REG_PAM2_OFFSET_Q35 0x92 // Programmable Attribute Map 2 > +#define REG_PAM3_OFFSET_Q35 0x93 // Programmable Attribute Map 3 > +#define REG_PAM4_OFFSET_Q35 0x94 // Programmable Attribute Map 4 > +#define REG_PAM5_OFFSET_Q35 0x95 // Programmable Attribute Map 5 > +#define REG_PAM6_OFFSET_Q35 0x96 // Programmable Attribute Map 6 > > #define PAM_BASE_ADDRESS 0xc0000 > #define PAM_LIMIT_ADDRESS BASE_1MB > -- > 2.7.0.windows.1 > _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
