On 24 March 2016 at 23:00, Ard Biesheuvel <ard.biesheu...@linaro.org> wrote:
> On 24 March 2016 at 21:30, Leo Duran <leo.du...@amd.com> wrote:
>> From: Leendert van Doorn <leend...@paramecium.org>
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: Leo Duran <leo.du...@amd.com>
>
> Reviewed-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
>
I have committed the following patches
f0bbcdf80df9 ArmPkg|EmbeddedPkg: make PcdCpuVectorBaseAddress 64 bits wide
91673dfdfe78 ArmPlatformPkg: fixups for 64-bit pointers
7e5a6e394c65 ArmPkg: apply Cortex-A57 errata
da6ae666410e EmbeddedPkg/RTC: use returned status at init-time
which correspond with 5 of the patches that you sent. The remaining
ones are either the responsibility of other maintainers, or require
further discussion.
Thanks,
Ard.
>> ---
>> ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c | 9 ++++++---
>> 1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
>> b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
>> index 135bd6b..3d39acd 100644
>> --- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
>> +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.c
>> @@ -40,12 +40,15 @@ ArmCpuSetup (
>> }
>>
>> //
>> - // If CPU is CortexA57 r0p0 apply Errata: 806969
>> + // If CPU is CortexA57 r0p0 apply Errata workarounds
>> //
>> if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==
>> ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {
>> - // DisableLoadStoreWB
>> - ArmSetCpuActlrBit (1ULL << 49);
>> +
>> + // Errata 806969: DisableLoadStoreWB (1ULL << 49)
>> + // Errata 813420: Execute Data Cache clean as Data Cache
>> clean/invalidate (1ULL << 44)
>> + // Errata 814670: disable DMB nullification (1ULL << 58)
>> + ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );
>> }
>> }
>>
>> --
>> 1.9.1
>>
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