The patch aligns to the IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe
driver not flush the UART in Reset() and SetAttributes() function.
It was found the flush causes hang on certain PCI serial devices.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <[email protected]>
Cc: Eric Jin <[email protected]>
---
 MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c | 27 +------------------------
 1 file changed, 1 insertion(+), 26 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c 
b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
index f1870f3..cce61d7 100644
--- a/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
+++ b/MdeModulePkg/Bus/Pci/PciSioSerialDxe/SerialIo.c
@@ -1,7 +1,7 @@
 /** @file
   SerialIo implementation for PCI or SIO UARTs.
 
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD 
License
 which accompanies this distribution.  The full text of the license may be 
found at
@@ -442,27 +442,6 @@ SerialReceiveTransmit (
   return EFI_SUCCESS;
 }
 
-/**
-  Flush the serial hardware transmit FIFO and shift register.
-
-  @param SerialDevice  The device to flush.
-**/
-VOID
-SerialFlushTransmitFifo (
-  SERIAL_DEV  *SerialDevice
-  )
-{
-  SERIAL_PORT_LSR  Lsr;
-
-  //
-  // Wait for the serial port to be ready, to make sure both the transmit FIFO
-  // and shift register empty.
-  //
-  do {
-    Lsr.Data = READ_LSR (SerialDevice);
-  } while (Lsr.Bits.Temt == 0);
-}
-
 //
 // Interface Functions
 //
@@ -503,8 +482,6 @@ SerialReset (
 
   Tpl = gBS->RaiseTPL (TPL_NOTIFY);
 
-  SerialFlushTransmitFifo (SerialDevice);
-
   //
   // Make sure DLAB is 0.
   //
@@ -683,8 +660,6 @@ SerialSetAttributes (
 
   Tpl = gBS->RaiseTPL (TPL_NOTIFY);
 
-  SerialFlushTransmitFifo (SerialDevice);
-
   //
   // Put serial port on Divisor Latch Mode
   //
-- 
2.7.0.windows.1

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