BTW, digging it a bit deeper and adding edk2-devel belatedly! For ARMv7 (assuming that is where the code was lifted from), it might be that the entire I$ was invaidated since it did the same to the branch predictor. The recommended sequence, as per the ARMv7 ARM, Section A3.5.4, should be:
DCCMVAU [instruction location] ; Clean data cache by MVA to point of unification DSB ; Ensure visibility of the data cleaned from the cache ICIMVAU [instruction location] ; Invalidate instruction cache by MVA to PoU BPIMVAU [instruction location] ; Invalidate branch predictor by MVA to PoU DSB ; Ensure completion of the invalidations ISB ; Synchronize fetched instruction stream thanks, Achin On Tue, May 10, 2016 at 09:46:03AM +0100, Achin Gupta wrote: > Thanks Eugene! Thought as much but wanted to be sure. I will put up something > for review in a bit. > > On Mon, May 09, 2016 at 10:53:52PM +0000, Cohen, Eugene wrote: > > > > Through the power of 'git blame' it looks like this dates back to the dawn > > of time (Andrew Fish and Olivier) and predates ARMv8. > > > > On AArch64 this is implemented thusly: > > > > ic iallu // Invalidate entire instruction cache > > dsb sy > > isb > > ret > > > > ARMv8 shows an IC IVAU at C5.4.11 so I think we can switch this to a cache > > range operation. > > > > Eugene > > > > > -----Original Message----- > > > From: Achin Gupta [mailto:[email protected]] > > > Sent: Monday, May 09, 2016 1:33 PM > > > To: Ard Biesheuvel <[email protected]>; Leif Lindholm > > > <[email protected]>; Cohen, Eugene <[email protected]> > > > Subject: I$ maintenance in ArmCacheMaintenanceLib.c > > > > > > Hi All, > > > > > > Does anyone of you know why on ARM platforms, the entire instruction > > > cache is invalidated in the following function : > > > > > > VOID * > > > EFIAPI > > > InvalidateInstructionCacheRange ( > > > IN VOID *Address, > > > IN UINTN Length > > > ) > > > { > > > CacheRangeOperation (Address, Length, > > > ArmCleanDataCacheEntryToPoUByMVA); > > > ArmInvalidateInstructionCache (); > > > return Address; > > > } > > > > > > Afaics, there is no instruction to perform a "IC IVAU" in > > > ArmPkg/Library/ArmLib/AArch64/AArch64Support.S. Instead of > > > ArmInvalidateInstructionCache() there should be another > > > CacheRangeOperation() for the ISide. > > > > > > There is another problem that CacheRangeOperation() caters for only > > > the Data cache line length even though the function name is generic. > > > > > > I am looking at the Tianocore edk2 tree (commit 9f64a83). Please let me > > > know if I am missing anything, else I will cook up some patches to fix the > > > problem. > > > > > > Thanks, > > > Achin > > > _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
