OK.
Reviewed-by: Maurice Ma <maurice...@intel.com>
-----Original Message-----
From: Leahy, Leroy P
Sent: Wednesday, May 11, 2016 1:36 PM
To: Ma, Maurice; edk2-devel@lists.01.org; Agyeman, Prince
Subject: RE: [PATCH 2/7] CorebootPayloadPkg: Assume no PCI serial devices
Hi Maurice,
This is the intent. The entire PCD needs to be present. If coreboot uses a
PCI device for its console then this PCD is written with the necessary values.
The first two bytes are set to the vendor and device ID values of the PCI
device that coreboot is using.
Lee Leahy
(425) 881-4919
Intel Corporation
Suite 125
2700 - 156th Ave NE
Bellevue, WA 98007-6554
-----Original Message-----
From: Ma, Maurice
Sent: Wednesday, May 11, 2016 11:16 AM
To: Leahy, Leroy P <leroy.p.le...@intel.com>; edk2-devel@lists.01.org; Agyeman,
Prince <prince.agye...@intel.com>
Subject: RE: [PATCH 2/7] CorebootPayloadPkg: Assume no PCI serial devices
Hi, Leah,
Is this list really consumed?
I saw the 0xffff terminator at the very beginning of the list. So it
indicates an empty list. Is this the intention?
Thanks
Maurice
-----Original Message-----
From: Leahy, Leroy P
Sent: Tuesday, May 10, 2016 3:34 PM
To: edk2-devel@lists.01.org; Leahy, Leroy P; Agyeman, Prince; Ma, Maurice
Subject: [PATCH 2/7] CorebootPayloadPkg: Assume no PCI serial devices
Set the vendor to 0xffff which indicates the end of the list.
Change-Id: If6475e04d3675f0a932571a85d1dd3f301416b6a
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.le...@intel.com>
---
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 4 ++--
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 907e952..cc88502 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -67,10 +67,10 @@
# UINT8 Reserved[2];
# } PCI_SERIAL_PARAMETER;
#
- # Vendor 0000 Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride = 1,
Clock 1843200 (0x1c2000)
+ # Vendor FFFF Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride
+ = 1, Clock 1843200 (0x1c2000)
#
# [Vendor] [Device]
[----ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo]
[TxFifo] [Rsvd] [Vendor]
- DEFINE PCI_SERIAL_PARAMETERS = {0x00,0x00, 0x00,0x00,
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0,
0x0,0x0, 0x0,0x0, 0xff,0xff}
+ DEFINE PCI_SERIAL_PARAMETERS = {0xff,0xff, 0x00,0x00,
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0,
0x0,0x0, 0x0,0x0, 0xff,0xff}
#
# Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI] diff --git
a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index 90a484d..77a33a9 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -67,10 +67,10 @@
# UINT8 Reserved[2];
# } PCI_SERIAL_PARAMETER;
#
- # Vendor 0000 Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride = 1,
Clock 1843200 (0x1c2000)
+ # Vendor FFFF Device 0000 Prog Interface 1, BAR #0, Offset 0, Stride
+ = 1, Clock 1843200 (0x1c2000)
#
# [Vendor] [Device]
[----ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo]
[TxFifo] [Rsvd] [Vendor]
- DEFINE PCI_SERIAL_PARAMETERS = {0x00,0x00, 0x00,0x00,
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0,
0x0,0x0, 0x0,0x0, 0xff,0xff}
+ DEFINE PCI_SERIAL_PARAMETERS = {0xff,0xff, 0x00,0x00,
0x0,0x20,0x1c,0x00, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x01, 0x0,0x0,
0x0,0x0, 0x0,0x0, 0xff,0xff}
#
# Shell options: [BUILD_SHELL, FULL_BIN, MIN_BIN, NONE, UEFI]
--
1.9.1
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