Reviewed by: [email protected]
> -----Original Message----- > From: Kinney, Michael D > Sent: Wednesday, May 18, 2016 3:08 AM > To: [email protected] > Cc: Fan, Jeff <[email protected]>; Yao, Jiewen <[email protected]>; > Tian, Feng <[email protected]> > Subject: [Patch V2 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Add SMRR > PhysBase/PhysMask fields check > > SMRR range size and alignment should follow the rules like MTRR: > a. The minimum range size is 4 KBytes and the base address of the > range must be on at least a 4-KByte boundary. > b. For ranges greater than 4 KBytes, each range must be of length > 2^n and its base address must be aligned on a 2^n boundary, where > n is a value equal to or greater than 12. The base-address > alignment value cannot be less than its length. > Thus, it could meet "Address_Within_Range AND PhysMask = PhysBase > AND PhysMask". > > Cc: Jeff Fan <[email protected]> > Cc: Jiewen Yao <[email protected]> > Cc: Feng Tian <[email protected]> > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Michael Kinney <[email protected]> > --- > .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 19 > ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > index 3e480e1..f525926 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > @@ -1,7 +1,7 @@ > /** @file > The CPU specific programming for PiSmmCpuDxeSmm module. > > -Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR> > +Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR> > This program and the accompanying materials > are licensed and made available under the terms and conditions of the BSD > License > which accompanies this distribution. The full text of the license may be > found at > @@ -245,6 +245,23 @@ SmmCpuFeaturesInitializeProcessor ( > // is protected and the normal mode code execution will fail. > // > if (mSmrrSupported) { > + // > + // SMRR size cannot be less than 4-KBytes > + // SMRR size must be of length 2^n > + // SMRR base alignment cannot be less than SMRR length > + // > + if ((CpuHotPlugData->SmrrSize < SIZE_4KB) || > + (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 > (CpuHotPlugData->SmrrSize)) || > + ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - > 1)) != CpuHotPlugData->SmrrBase)) { > + // > + // Print message if CPU is BSP > + // > + if ((ProcessorInfo->StatusFlag & PROCESSOR_AS_BSP_BIT) != 0) { > + DEBUG ((EFI_D_ERROR, "SMM Base/Size does not meet > alignment/size requirement!\n")); > + } > + CpuDeadLoop (); > + } > + > AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | > MTRR_CACHE_WRITE_BACK); > AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - > 1) & EFI_MSR_SMRR_MASK)); > mSmrrEnabled[CpuIndex] = FALSE; > -- > 2.6.3.windows.1 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
