>From Intel(R) 64 and IA-32 Architectures Software Developer's Manual, one lock or semaphore is suggested to be present within a cache line. If the processors are based on Intel NetBurst microarchitecture, two cache lines are suggested. This could minimize the bus traffic required to service locks.
This serial of patches makes use of the upper requirement to improve SMI handler performance. Jeff Fan (7): UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for global semaphores UefiCpuPkg/PiSmmCpuDxeSmm: Move forward MP sync data initialization UefiCpuPkg/PiSmmCpuDxeSmm: Using global semaphores in aligned buffer UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for each CPU semaphores UefiCpuPkg/PiSmmCpuDxeSmm: Using CPU semaphores in aligned buffer UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for MSRs semaphores UefiCpuPkg/PiSmmCpuDxeSmm: Using MSRs semaphores in aligned buffer UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 35 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 10 +- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 212 ++++++++++++++++++++--------- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 20 +-- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 58 +++++++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 9 +- 6 files changed, 243 insertions(+), 101 deletions(-) -- 2.6.3.windows.1 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
