Cc: Michael Kinney <[email protected]>
Cc: Feng Tian <[email protected]>
Cc: Giri P Mudusuru <[email protected]>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <[email protected]>
---
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 51 ++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index 6695b69..75f2dce 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -41,6 +41,7 @@
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
@endcode
+ @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
**/
#define MSR_XEON_PHI_SMI_COUNT 0x00000034
@@ -85,6 +86,7 @@ typedef union {
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
@endcode
+ @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
**/
#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
@@ -151,6 +153,7 @@ typedef union {
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
@endcode
+ @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as
MSR_PKG_CST_CONFIG_CONTROL in SDM.
**/
#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
@@ -208,6 +211,7 @@ typedef union {
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
@endcode
+ @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE
in SDM.
**/
#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
@@ -261,6 +265,7 @@ typedef union {
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
@endcode
+ @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
**/
#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
@@ -313,6 +318,7 @@ typedef union {
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
@endcode
+ @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
**/
#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
@@ -402,6 +408,7 @@ typedef union {
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
@endcode
+ @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET
in SDM.
**/
#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
@@ -450,6 +457,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
@endcode
+ @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
**/
#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
@@ -468,6 +476,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
@endcode
+ @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
**/
#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
@@ -488,6 +497,7 @@ typedef union {
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
@endcode
+ @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in
SDM.
**/
#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
@@ -612,6 +622,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
@endcode
+ @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
**/
#define MSR_XEON_PHI_LBR_SELECT 0x000001C8
@@ -630,6 +641,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
@endcode
+ @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
**/
#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
@@ -647,6 +659,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
@endcode
+ @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
**/
#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
@@ -664,6 +677,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
@endcode
+ @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
**/
#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
@@ -682,6 +696,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);
AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);
@endcode
+ @note MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS is defined as
IA32_PERF_GLOBAL_STAUS in SDM.
**/
#define MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS 0x0000038E
@@ -700,6 +715,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
@endcode
+ @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
**/
#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
@@ -720,6 +736,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
@endcode
+ @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in
SDM.
**/
#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
@@ -738,6 +755,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
@endcode
+ @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in
SDM.
**/
#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
@@ -756,6 +774,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
@endcode
+ @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in
SDM.
**/
#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
@@ -776,6 +795,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
@endcode
+ @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.
**/
#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
@@ -794,6 +814,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
@endcode
+ @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.
**/
#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
@@ -814,6 +835,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
@endcode
+ @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in
SDM.
**/
#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
@@ -832,6 +854,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_CTL);
AsmWriteMsr64 (MSR_XEON_PHI_MC3_CTL, Msr);
@endcode
+ @note MSR_XEON_PHI_MC3_CTL is defined as MSR_MC3_CTL in SDM.
**/
#define MSR_XEON_PHI_MC3_CTL 0x0000040C
@@ -850,6 +873,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_STATUS);
AsmWriteMsr64 (MSR_XEON_PHI_MC3_STATUS, Msr);
@endcode
+ @note MSR_XEON_PHI_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
**/
#define MSR_XEON_PHI_MC3_STATUS 0x0000040D
@@ -868,6 +892,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_ADDR);
AsmWriteMsr64 (MSR_XEON_PHI_MC3_ADDR, Msr);
@endcode
+ @note MSR_XEON_PHI_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
**/
#define MSR_XEON_PHI_MC3_ADDR 0x0000040E
@@ -886,6 +911,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_CTL);
AsmWriteMsr64 (MSR_XEON_PHI_MC4_CTL, Msr);
@endcode
+ @note MSR_XEON_PHI_MC4_CTL is defined as MSR_MC4_CTL in SDM.
**/
#define MSR_XEON_PHI_MC4_CTL 0x00000410
@@ -904,6 +930,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_STATUS);
AsmWriteMsr64 (MSR_XEON_PHI_MC4_STATUS, Msr);
@endcode
+ @note MSR_XEON_PHI_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
**/
#define MSR_XEON_PHI_MC4_STATUS 0x00000411
@@ -925,6 +952,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_ADDR);
AsmWriteMsr64 (MSR_XEON_PHI_MC4_ADDR, Msr);
@endcode
+ @note MSR_XEON_PHI_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
**/
#define MSR_XEON_PHI_MC4_ADDR 0x00000412
@@ -943,6 +971,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_CTL);
AsmWriteMsr64 (MSR_XEON_PHI_MC5_CTL, Msr);
@endcode
+ @note MSR_XEON_PHI_MC5_CTL is defined as MSR_MC5_CTL in SDM.
**/
#define MSR_XEON_PHI_MC5_CTL 0x00000414
@@ -961,6 +990,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_STATUS);
AsmWriteMsr64 (MSR_XEON_PHI_MC5_STATUS, Msr);
@endcode
+ @note MSR_XEON_PHI_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
**/
#define MSR_XEON_PHI_MC5_STATUS 0x00000415
@@ -979,6 +1009,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_ADDR);
AsmWriteMsr64 (MSR_XEON_PHI_MC5_ADDR, Msr);
@endcode
+ @note MSR_XEON_PHI_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
**/
#define MSR_XEON_PHI_MC5_ADDR 0x00000416
@@ -996,6 +1027,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
@endcode
+ @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as
IA32_VMX_EPT_VPID_ENUM in SDM.
**/
#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
@@ -1014,6 +1046,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
@endcode
+ @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
**/
#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
@@ -1033,6 +1066,7 @@ typedef union {
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
@endcode
+ @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
**/
#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
@@ -1092,6 +1126,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
@endcode
+ @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in
SDM.
**/
#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
@@ -1111,6 +1146,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
@endcode
+ @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
**/
#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
@@ -1128,6 +1164,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
@endcode
+ @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in
SDM.
**/
#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
@@ -1145,6 +1182,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
@endcode
+ @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
**/
#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
@@ -1164,6 +1202,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
@endcode
+ @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
**/
#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
@@ -1183,6 +1222,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
@endcode
+ @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in
SDM.
**/
#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
@@ -1200,6 +1240,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
@endcode
+ @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS
in SDM.
**/
#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
@@ -1218,6 +1259,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
@endcode
+ @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in
SDM.
**/
#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
@@ -1236,6 +1278,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
@endcode
+ @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
**/
#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
@@ -1255,6 +1298,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
@endcode
+ @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
**/
#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
@@ -1273,6 +1317,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
@endcode
+ @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in
SDM.
**/
#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
@@ -1290,6 +1335,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
@endcode
+ @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL
in SDM.
**/
#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
@@ -1307,6 +1353,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
@endcode
+ @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in
SDM.
**/
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
@@ -1324,6 +1371,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
@endcode
+ @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in
SDM.
**/
#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
@@ -1342,6 +1390,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
@endcode
+ @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL
in SDM.
**/
#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
@@ -1360,6 +1409,7 @@ typedef union {
Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
@endcode
+ @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as
MSR_TURBO_ACTIVATION_RATIO in SDM.
**/
#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
@@ -1381,6 +1431,7 @@ typedef union {
Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
@endcode
+ @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as
MSR_CORE_PERF_LIMIT_REASONS in SDM.
**/
#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
--
2.9.3.windows.2
_______________________________________________
edk2-devel mailing list
[email protected]
https://lists.01.org/mailman/listinfo/edk2-devel
