2016-09-22 18:03 GMT+03:00, Ard Biesheuvel <ard.biesheu...@linaro.org>:
> On 22 September 2016 at 15:30, valerij zaporogeci <vlrzpr...@gmail.com>
> wrote:
>> In the ARM architecture, there is such a thing - "flat mapping", where
>> MMU stage 1 is disabled and the mapping done is 1:1 and attributes set
>> to the predefined values.
> What do you mean by 'attributes set to the predefined values' ?

I meant what is written in the section B3.2.1, short quote:
"For all other accesses, when a stage 1 MMU is disabled, the assigned
attributes depend on whether
the access is a data access or an instruction access, as follows:
Data access
The stage 1 translation assigns the Strongly-Ordered memory type"

... and then, more lengthy description for instruction access.

> On ARM, you need to enable the MMU in order to enable the Dcache.

Thank you, I suspected this is for this, just wanted to be sure.
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