> On Sep 22, 2016, at 8:03 AM, Ard Biesheuvel <ard.biesheu...@linaro.org> wrote:
> 
> On 22 September 2016 at 15:30, valerij zaporogeci <vlrzpr...@gmail.com 
> <mailto:vlrzpr...@gmail.com>> wrote:
>> In the ARM architecture, there is such a thing - "flat mapping", where
>> MMU stage 1 is disabled and the mapping done is 1:1 and attributes set
>> to the predefined values.
> 
> What do you mean by 'attributes set to the predefined values' ?
> 
>> Did I understand right, that this is NOT what UEFI means by "identity
>> mapping" with MMU enabled?

Identity mapping means the virtual address is the same as the physical address. 

For x86 IA64 (x86_64) you have to have paging enabled to enter long (64-bit) 
mode (the processor comes out of reset in 16-bit mode). For ARM you need the 
MMU to control cacheability.

For IA32 (i386) paging is not enabled and MTRR registers are used to control 
cacheability. For Itainium Processors paging is not enabled and bit 63 is used 
to disable cacheability.

Thanks,

Andrew Fish

>> And in the latter case there is need to
>> create all those page tables and stuff, setting 1:1 mapping between VA
>> and PA? If so, why to do that? Why "flat mapping" isn't what UEFI
>> would love to see as its mapping regime?
> 
> On ARM, you need to enable the MMU in order to enable the Dcache.
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