Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
On 2017-01-06 09:28:47, Laszlo Ersek wrote: > EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE expects the PCI address to > access in UEFI encoding, not in edk2/PciLib encoding. > > Introduce the POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS() macro, and with > it, store the ICH9_GEN_PMCON_1 register's address to the boot script in > UEFI representation. > > Cc: Jiewen Yao <jiewen....@intel.com> > Cc: Jordan Justen <jordan.l.jus...@intel.com> > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Laszlo Ersek <ler...@redhat.com> > --- > > Notes: > v2: > - replace ConvertPciLibToEfiPciAddress() with > POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS() [Jordan, Jiewen] > > OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 6 ++++++ > OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c | 5 ++++- > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h > b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h > index 4dc2c39901c1..f480455ae432 100644 > --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h > +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h > @@ -19,6 +19,9 @@ > #define __Q35_MCH_ICH9_H__ > > #include <Library/PciLib.h> > +#include <Uefi/UefiBaseType.h> > +#include <Uefi/UefiSpec.h> > +#include <Protocol/PciRootBridgeIo.h> > > // > // Host Bridge Device ID (DID) value for Q35/MCH > @@ -75,6 +78,9 @@ > #define POWER_MGMT_REGISTER_Q35(Offset) \ > PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset)) > > +#define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \ > + EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset)) > + > #define ICH9_PMBASE 0x40 > #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | > \ > BIT10 | BIT9 | BIT8 | BIT7) > diff --git a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c > b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c > index 82549b0a7e35..6c03e17a3a8d 100644 > --- a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c > +++ b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c > @@ -311,6 +311,7 @@ OnS3SaveStateInstalled ( > EFI_STATUS Status; > EFI_S3_SAVE_STATE_PROTOCOL *S3SaveState; > UINT32 SmiEnOrMask, SmiEnAndMask; > + UINT64 GenPmCon1Address; > UINT16 GenPmCon1OrMask, GenPmCon1AndMask; > > ASSERT (Event == mS3SaveStateInstalled); > @@ -342,13 +343,15 @@ OnS3SaveStateInstalled ( > CpuDeadLoop (); > } > > + GenPmCon1Address = POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS ( > + ICH9_GEN_PMCON_1); > GenPmCon1OrMask = ICH9_GEN_PMCON_1_SMI_LOCK; > GenPmCon1AndMask = MAX_UINT16; > Status = S3SaveState->Write ( > S3SaveState, > EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE, > EfiBootScriptWidthUint16, > - (UINT64)POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1), > + GenPmCon1Address, > &GenPmCon1OrMask, > &GenPmCon1AndMask > ); > -- > 2.9.3 > _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
