Reviewed-by: zwei4 <david....@intel.com>
Thanks,
David Wei
-----Original Message-----
From: Guo, Mang
Sent: Thursday, February 16, 2017 11:37 AM
To: edk2-devel@lists.01.org
Cc: Wei, David <david....@intel.com>; Lu, ShifeiX A <shifeix.a...@intel.com>
Subject: [Patch][edk2-platforms/devel-MinnowBoard3] Fix MRC restore issue
MCR parameter restored in the second time of boot, so the boot time is less
than the first time of boot.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang....@intel.com>
---
.../LeafHill/BoardInitPreMem/BoardInitMiscs.c | 17 +++++++++++++--
.../LeafHill/BoardInitPreMem/BoardInitPreMem.inf | 1 +
.../MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c | 17 +++++++++++++--
.../BoardInitPreMem/BoardInitPreMem.inf | 1 +
.../BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h | 2 ++
.../MemoryInit/BXT/Include/MrcEfiDefinitions.h | 3 ++-
.../Mmrc/ProjectIndependent/Include/MmrcData.h | 24 +++++++++++++++++++++-
7 files changed, 59 insertions(+), 6 deletions(-)
diff --git
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
index 5af2fae..fe8ece0 100644
---
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
+++
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitMiscs.c
@@ -14,6 +14,7 @@
**/
#include "BoardInitMiscs.h"
+#include "MmrcData.h"
UPDATE_FSPM_UPD_FUNC mLhUpdateFspmUpdPtr = LhUpdateFspmUpd;
DRAM_CREATE_POLICY_DEFAULTS_FUNC mLhDramCreatePolicyDefaultsPtr =
LhDramCreatePolicyDefaults;
@@ -29,6 +30,9 @@ LhUpdateFspmUpd (
EFI_PLATFORM_INFO_HOB *PlatformInfo = NULL;
DRAM_POLICY_PPI *DramPolicy;
EFI_STATUS Status;
+ MRC_NV_DATA_FRAME *MrcNvData;
+ MRC_PARAMS_SAVE_RESTORE *MrcParamsHob;
+ BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob;
Status = (*PeiServices)->LocatePpi (
PeiServices,
@@ -64,11 +68,20 @@ LhUpdateFspmUpd (
FspUpdRgn->FspmConfig.InterleavedMode =
DramPolicy->InterleavedMode;
FspUpdRgn->FspmConfig.MinRefRate2xEnable =
DramPolicy->MinRefRate2xEnabled;
FspUpdRgn->FspmConfig.DualRankSupportEnable =
DramPolicy->DualRankSupportEnabled;
- FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID
*)(UINT32)DramPolicy->MrcTrainingDataPtr;
- FspUpdRgn->FspmConfig.MrcBootDataPtr = (VOID
*)(UINT32)DramPolicy->MrcBootDataPtr;
CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp,
sizeof (DramPolicy->ChDrp));
CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling),
&DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle));
+
+ if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&
+ ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr != 0)) {
+ MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof
(MRC_NV_DATA_FRAME));
+ MrcParamsHob =
(MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);
+ BootVariableNvDataHob =
(BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);
+ CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof
(MRC_PARAMS_SAVE_RESTORE));
+ CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof
(BOOT_VARIABLE_NV_DATA));
+ FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;
+ }
+
}
//
// override RankEnable settings for Minnow
diff --git
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf
index c170839..c526bc2 100644
---
a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf
+++
b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/BoardInitPreMem.inf
@@ -39,6 +39,7 @@
IntelFsp2Pkg/IntelFsp2Pkg.dec
BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec
[Pcd]
gPlatformModuleTokenSpaceGuid.PcdBoardId
diff --git
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c
index ece8a88..9e535ca 100644
---
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c
+++
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitMiscs.c
@@ -14,6 +14,7 @@
**/
#include "BoardInitMiscs.h"
+#include "MmrcData.h"
UPDATE_FSPM_UPD_FUNC mMb3UpdateFspmUpdPtr = Mb3UpdateFspmUpd;
DRAM_CREATE_POLICY_DEFAULTS_FUNC mMb3DramCreatePolicyDefaultsPtr =
Mb3DramCreatePolicyDefaults;
@@ -29,6 +30,9 @@ Mb3UpdateFspmUpd (
EFI_PLATFORM_INFO_HOB *PlatformInfo = NULL;
DRAM_POLICY_PPI *DramPolicy;
EFI_STATUS Status;
+ MRC_NV_DATA_FRAME *MrcNvData;
+ MRC_PARAMS_SAVE_RESTORE *MrcParamsHob;
+ BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob;
Status = (*PeiServices)->LocatePpi (
PeiServices,
@@ -64,11 +68,20 @@ Mb3UpdateFspmUpd (
FspUpdRgn->FspmConfig.InterleavedMode =
DramPolicy->InterleavedMode;
FspUpdRgn->FspmConfig.MinRefRate2xEnable =
DramPolicy->MinRefRate2xEnabled;
FspUpdRgn->FspmConfig.DualRankSupportEnable =
DramPolicy->DualRankSupportEnabled;
- FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID
*)(UINT32)DramPolicy->MrcTrainingDataPtr;
- FspUpdRgn->FspmConfig.MrcBootDataPtr = (VOID
*)(UINT32)DramPolicy->MrcBootDataPtr;
CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp,
sizeof(DramPolicy->ChDrp));
CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling),
&DramPolicy->ChSwizzle, sizeof (DramPolicy->ChSwizzle));
+
+ if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr != 0) &&
+ ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr != 0)) {
+ MrcNvData = (MRC_NV_DATA_FRAME *) AllocateZeroPool (sizeof
(MRC_NV_DATA_FRAME));
+ MrcParamsHob =
(MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPolicy->MrcTrainingDataPtr);
+ BootVariableNvDataHob =
(BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolicy->MrcBootDataPtr);
+ CopyMem(&(MrcNvData->MrcParamsSaveRestore), MrcParamsHob, sizeof
(MRC_PARAMS_SAVE_RESTORE));
+ CopyMem(&(MrcNvData->BootVariableNvData), BootVariableNvDataHob, sizeof
(BOOT_VARIABLE_NV_DATA));
+ FspUpdRgn->FspmArchUpd.NvsBufferPtr = (VOID *)(UINT32)MrcNvData;
+ }
+
}
//
// override RankEnable settings for Minnow
diff --git
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf
index f64ab8f..9135fb8 100644
---
a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf
+++
b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/BoardInitPreMem.inf
@@ -39,6 +39,7 @@
IntelFsp2Pkg/IntelFsp2Pkg.dec
BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ Silicon\BroxtonSoC\BroxtonSiPkg\NorthCluster\MemoryInit\MemoryInit.dec
[Pcd]
gPlatformModuleTokenSpaceGuid.PcdBoardId
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h
b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h
index 7eb0e92..a2da161 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Ppi/DramPolicyPpi.h
@@ -56,10 +56,12 @@ typedef struct {
UINT8 RmtMode;
UINT8 RmtCheckRun;
UINT16 RmtMarginCheckScaleHighThreshold;
+ UINT8 Reserved1;
UINT32 MsgLevelMask;
UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES];
UINT8
ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];
DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS];
+ UINT8 Reserved2;
UINT8 DebugMsgLevel;
UINT8 reserved[13];
} DRAM_POLICY_PPI;
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
index b19d6a0..5d36a6d 100644
---
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
+++
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/BXT/Include/MrcEfiDefinitions.h
@@ -64,10 +64,12 @@ typedef struct {
UINT8 RmtMode;
UINT8 RmtCheckRun;
UINT16 RmtMarginCheckScaleHighThreshold;
+ UINT8 Reserved1;
UINT32 MsgLevelMask;
UINT8 SpdAddress[DRAM_POLICY_NUMBER_SPD_ADDRESSES];
UINT8
ChSwizzle[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS];
DRP_DRAM_POLICY ChDrp[DRAM_POLICY_NUMBER_CHANNELS];
+ UINT8 Reserved2;
UINT8 DebugMsgLevel;
UINT8 reserved[13];
} DRAM_POLICY_PPI;
@@ -79,7 +81,6 @@ typedef struct {
typedef enum {
Bxt = 0x00,
Bxt1,
- BxtX,
BxtP,
BxtSeriesMax = 0xFF
} BXT_SERIES;
diff --git
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
index 0d64528..eb0f973 100644
---
a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
+++
b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/Mmrc/ProjectIndependent/Include/MmrcData.h
@@ -52,6 +52,25 @@ typedef union {
UINT8 Data8[4];
} MrcVersion;
+typedef union {
+ UINT8 Data;
+ struct {
+
+ UINT8 RankSelectInterleavingEnable : 1;
+
+ UINT8 BankAddressHashingEnable : 1;
+
+ UINT8 Ch1ClkDisable : 1;
+
+ UINT8 Reserved : 1;
+
+ UINT8 AddressMapping : 2;
+
+ UINT8 Reserved0 : 2;
+ } Bits;
+} CHANNEL_OPTION;
+
+
#ifndef ABSOLUTE
#define ABSOLUTE 1
#define RELATIVE 2
@@ -104,6 +123,9 @@ typedef enum {
#define BIT31 0x80000000
#endif
+
+#pragma pack(1)
+
typedef enum {
Pfct = 0,
PfctT,
@@ -212,6 +234,7 @@ typedef struct {
UINT8 OdtHigh;
UINT16 LP4_MR0VALUE;
UINT16 LP4_MR4VALUE;
+ CHANNEL_OPTION ChOption;
} CHANNEL;
typedef struct {
@@ -242,7 +265,6 @@ typedef struct {
BOOT_VARIABLE_NV_DATA BootVariableNvData;
} MRC_NV_DATA_FRAME;
-#pragma pack()
#pragma pack(pop)
#endif
--
2.10.1.windows.1
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