On Thu, Apr 06, 2017 at 02:15:47PM +0100, Ard Biesheuvel wrote: > The VRAM of the PL111 on the FVP Base/Foundation models is described as > device memory rather than uncached memory, which is not an accurate > description of the nature of the region (i.e., a framebuffer), and may > result in problems when using accelerated string routines to access the > region, since this may legally involve unaligned accesses or DC ZVA > instructions, which are not allowed on device mappings. > > So split of the 8 MB VRAM region into a separate region, and map it using > memory attributes.
"Normal memory attributes"? > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel <[email protected]> > --- > ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h | 10 > ++++++---- > ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 8 > +++++++- > 2 files changed, 13 insertions(+), 5 deletions(-) > > diff --git > a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h > b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h > index 06414e6e7208..4e17c800a34f 100644 > --- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h > +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h > @@ -40,9 +40,11 @@ > #define ARM_VE_SMB_SRAM_BASE 0x2E000000 > #define ARM_VE_SMB_SRAM_SZ SIZE_64KB > // USB, Ethernet, VRAM > -#define ARM_VE_SMB_PERIPH_BASE 0x18000000 > -#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE > -#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB > +#define ARM_VE_SMB_PERIPH_BASE 0x18800000 > +#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB) > + > +#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000 > +#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE SIZE_8MB > > // DRAM > #define ARM_VE_DRAM_BASE PcdGet64 > (PcdSystemMemoryBase) > @@ -75,6 +77,6 @@ > #define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1 > > // VRAM offset for the PL111 Colour LCD Controller on the motherboard > -#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE > + 0x00000) > +#define VRAM_MOTHERBOARD_BASE > (PL111_CLCD_VRAM_MOTHERBOARD_BASE) > > #endif > diff --git > a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > index 14c7e8e1d672..70c17ae70478 100644 > --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > @@ -21,7 +21,7 @@ > #include <ArmPlatform.h> > > // Number of Virtual Memory Map Descriptors > -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8 > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 > > // DDR attributes > #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK > @@ -130,6 +130,12 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; > VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > > + // VRAM > + VirtualMemoryTable[++Index].PhysicalBase = > PL111_CLCD_VRAM_MOTHERBOARD_BASE; > + VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; > + VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE; > + VirtualMemoryTable[Index].Attributes = > ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; Hmm, looking at this made me a bit confused though. Normal uncached memory is certainly bufferable (that's basically what write-combining means). This looks like a naming hangover from ARMv5 translation table format. Is it about time we clean this up? Or have I sprained my brain? / Leif > + > // Map sparse memory region if present > if (HasSparseMemory) { > VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase; > -- > 2.9.3 > _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
