Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <[email protected]> Cc: Jeff Fan <[email protected]> --- UefiCpuPkg/Include/Register/Msr.h | 1 + UefiCpuPkg/Include/Register/Msr/XeonE5v2Msr.h | 91 +++++++++++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 UefiCpuPkg/Include/Register/Msr/XeonE5v2Msr.h
diff --git a/UefiCpuPkg/Include/Register/Msr.h b/UefiCpuPkg/Include/Register/Msr.h index 0ac8d5b..8dbd6f7 100644 --- a/UefiCpuPkg/Include/Register/Msr.h +++ b/UefiCpuPkg/Include/Register/Msr.h @@ -45,5 +45,6 @@ #include <Register/Msr/PentiumMMsr.h> #include <Register/Msr/P6Msr.h> #include <Register/Msr/PentiumMsr.h> +#include <Register/Msr/XeonE5v2Msr.h> #endif diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE5v2Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE5v2Msr.h new file mode 100644 index 0000000..29ba125 --- /dev/null +++ b/UefiCpuPkg/Include/Register/Msr/XeonE5v2Msr.h @@ -0,0 +1,91 @@ +/** @file + MSR Definitions for Intel(R) Xeon(R) Processor E5 v2 Family. + + Provides defines for Machine Specific Registers(MSR) indexes. Data structures + are provided for MSRs that contain one or more bit fields. If the MSR value + returned is a single 32-bit or 64-bit value, then a data structure is not + provided for that MSR. + + Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, + September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8. + +**/ + +#ifndef __XEON_E5_V2_MSR_H__ +#define __XEON_E5_V2_MSR_H__ + +#include <Register/ArchitecturalMsr.h> + +/** + Is Intel(R) Xeon(R) Processor E5 V2 Family? + + @param DisplayFamily Display Family ID + @param DisplayModel Display Model ID + + DisplayModel == 0x3E Intel Xeon processors E5 V2 + + @retval TRUE Yes, it is. + @retval FALSE No, it isn't. +**/ +#define IS_XEON_E5_V2_PROCESSOR(DisplayFamily, DisplayModel) \ + (DisplayFamily == 0x06 && \ + ( \ + DisplayModel == 0x3E \ + ) \ + ) + +#define MSR_XEON_E5_V2_PIN_CTL 0x0000004E + +/** + MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LockOut (R/WO) 1 = Locked; 0 = unlocked + /// Set 1 to prevent further writes to MSR_PPIN_CTL. Writing 1 to + /// MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit 1] is + /// clear, Default is 0. + /// BIOS should provide an opt-in menu to enable the user to turn on + /// MSR_PPIN_CTL[bit 1] for privileged inventory initialization agent to + /// access MSR_PPIN. After reading MSR_PPIN, the privileged + /// inventory initialization agent should write '1b' to MSR_PPIN_CTL + /// to disable further access to MSR_PPIN and prevent unauthorized + /// modification to MSR_PPIN_CTL + /// + UINT32 LockOut:1; + /// [Bit 1] Enable_PPIN (R/W) 1 = Enabled; 0 = Disabled + /// If 1, enables MSR_PPIN to be accessible using RDMSR. Once set, + /// attempt to write 1 to MSR_PPIN_CTL[bit 0] will cause #GP. + /// If 0, an attempt to read MSR_PPIN will cause #GP. Default is 0 + /// + UINT32 EnablePpin:1; + UINT32 Reserved1:30; + UINT32 Reserved2:32; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_XEON_E5_V2_PIN_CTL_REGISTER; + +#define MSR_XEON_E5_V2_PLATFORM_INFO 0x000000CE + +#endif \ No newline at end of file -- 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
