As HOB which has 8byte aligned requirement will be built based on them in PEI phase.
Cc: Liming Gao <[email protected]> Cc: Jeff Fan <[email protected]> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <[email protected]> --- UefiCpuPkg/SecCore/SecMain.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c index 077d0db49f53..a53fa04cc303 100644 --- a/UefiCpuPkg/SecCore/SecMain.c +++ b/UefiCpuPkg/SecCore/SecMain.c @@ -1,7 +1,7 @@ /** @file C functions in SEC - Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -230,6 +230,11 @@ SecStartupPhase2( ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI_DESCRIPTOR)); SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR)); SecCoreData->PeiTemporaryRamSize = SecCoreData->PeiTemporaryRamSize - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR); + // + // Adjust the Base and Size to be 8-byte aligned. + // + SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07); + SecCoreData->PeiTemporaryRamSize &= ~0x07; } else { // // No addition PPI, PpiList directly point to the common PPI list. -- 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
