Hi, Some comments below.
On 25 August 2017 at 09:57, Ruiyu Ni <[email protected]> wrote: > The patch adds two PciSegmentLib instances that consumes > PciSegmentInfoLib to provide multiple segments PCI configuration > access. > > BasePciSegmentLibSegmentInfo instance is a BASE library. > DxeRuntimePciSegmentLibSegmentInfo instance is to be linked with > runtime drivers to provide not only boot time but also runtime > PCI configuration access. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ruiyu Ni <[email protected]> > Cc: Liming Gao <[email protected]> > --- > .../PciSegmentLibSegmentInfo/BasePciSegmentLib.c | 71 + > .../BasePciSegmentLibSegmentInfo.inf | 46 + > .../BasePciSegmentLibSegmentInfo.uni | 21 + > .../DxeRuntimePciSegmentLib.c | 321 +++++ > .../DxeRuntimePciSegmentLibSegmentInfo.inf | 55 + > .../DxeRuntimePciSegmentLibSegmentInfo.uni | 21 + > .../PciSegmentLibSegmentInfo/PciSegmentLibCommon.c | 1375 > ++++++++++++++++++++ > .../PciSegmentLibSegmentInfo/PciSegmentLibCommon.h | 57 + > MdePkg/MdePkg.dsc | 2 + > 9 files changed, 1969 insertions(+) > create mode 100644 > MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLib.c > create mode 100644 > MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf > create mode 100644 > MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.uni > create mode 100644 > MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLib.c > create mode 100644 > MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf > create mode 100644 > MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.uni > create mode 100644 > MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c > create mode 100644 > MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.h > [...] > diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c > b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c > new file mode 100644 > index 0000000000..7b7324d673 > --- /dev/null > +++ b/MdePkg/Library/PciSegmentLibSegmentInfo/PciSegmentLibCommon.c > @@ -0,0 +1,1375 @@ > +/** @file > + Provide common routines used by BasePciSegmentLibSegmentInfo and > + DxeRuntimePciSegmentLibSegmentInfo libraries. > + > + Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> > + This program and the accompanying materials are > + licensed and made available under the terms and conditions of > + the BSD License which accompanies this distribution. The full > + text of the license may be found at > + http://opensource.org/licenses/bsd-license.php. > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > IMPLIED. > + > +**/ > + > +#include "PciSegmentLibCommon.h" > + > +typedef struct { > + UINT64 Register : 12; > + UINT64 Function : 3; > + UINT64 Device : 5; > + UINT64 Bus : 8; > + UINT64 Reserved1 : 4; > + UINT64 Segment : 16; > + UINT64 Reserved2 : 16; > +} PCI_SEGMENT_LIB_ADDRESS_STRUCTURE; > + Is this guaranteed to work as expected by the C spec? > +/** > + Internal function that converts PciSegmentLib format address that encodes > the PCI Bus, Device, > + Function and Register to ECAM (Enhanced Configuration Access Mechanism) > address. > + > + @param Address The address that encodes the PCI Bus, Device, Function > and > + Register. > + @param SegmentInfo An array of PCI_SEGMENT_INFO holding the segment > information. > + @param Count Number of segments. > + > + @retval ECAM address. > +**/ > +UINTN > +PciSegmentLibGetEcamAddress ( > + IN UINT64 Address, > + IN CONST PCI_SEGMENT_INFO *SegmentInfo, > + IN UINTN Count > + ) > +{ > + while (Count != 0) { > + if (SegmentInfo->SegmentNumber == ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE > *)&Address)->Segment) { > + break; > + } > + SegmentInfo++; > + Count--; > + } > + ASSERT (Count != 0); > + ASSERT ( > + (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved1 == 0) && > + (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved2 == 0) > + ); > + ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus >= > SegmentInfo->StartBusNumber); > + ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus <= > SegmentInfo->EndBusNumber); > + > + Address = SegmentInfo->BaseAddress + PCI_ECAM_ADDRESS ( > + ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus, > + ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Device, > + ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Function, > + ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Register); > + > + if (sizeof (UINTN) == sizeof (UINT32)) { > + ASSERT (Address < BASE_4GB); > + } > + > + return PciSegmentLibVirtualAddress ((UINTN)Address); > +} > + > +/** > + Reads an 8-bit PCI configuration register. > + > + Reads and returns the 8-bit PCI configuration register specified by > Address. > + This function must guarantee that all PCI read and write operations are > serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + > + @return The 8-bit PCI configuration register specified by Address. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentRead8 ( > + IN UINT64 Address > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count)); > +} > + > +/** > + Writes an 8-bit PCI configuration register. > + > + Writes the 8-bit PCI configuration register specified by Address with the > value specified by Value. > + Value is returned. This function must guarantee that all PCI read and > write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param Value The value to write. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentWrite8 ( > + IN UINT64 Address, > + IN UINT8 Value > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), Value); > +} > + > +/** > + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit > value. > + > + Reads the 8-bit PCI configuration register specified by Address, > + performs a bitwise OR between the read result and the value specified by > OrData, > + and writes the result to the 8-bit PCI configuration register specified by > Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentOr8 ( > + IN UINT64 Address, > + IN UINT8 OrData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), > OrData); > +} > + > +/** > + Performs a bitwise AND of an 8-bit PCI configuration register with an > 8-bit value. > + > + Reads the 8-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by > AndData, > + and writes the result to the 8-bit PCI configuration register specified by > Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > serialized. > + If any reserved bits in Address are set, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentAnd8 ( > + IN UINT64 Address, > + IN UINT8 AndData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioAnd8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), AndData); > +} > + > +/** > + Performs a bitwise AND of an 8-bit PCI configuration register with an > 8-bit value, > + followed a bitwise OR with another 8-bit value. > + > + Reads the 8-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by > AndData, > + performs a bitwise OR between the result of the AND operation and the > value specified by OrData, > + and writes the result to the 8-bit PCI configuration register specified by > Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param AndData The value to AND with the PCI configuration register. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentAndThenOr8 ( > + IN UINT64 Address, > + IN UINT8 AndData, > + IN UINT8 OrData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), AndData, OrData); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in an 8-bit PCI configuration register. The bit field > is > + specified by the StartBit and the EndBit. The value of the bit field is > + returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param Address PCI configuration register to read. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..7. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + > + @return The value of the bit field read from the PCI configuration > register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldRead8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldRead8 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 8-bit register is returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If Value is larger than the bitmask value range specified by StartBit and > EndBit, then ASSERT(). > + > + @param Address PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..7. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param Value New value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldWrite8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 Value > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldWrite8 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit, Value); > +} > + > +/** > + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and > + writes the result back to the bit field in the 8-bit port. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 8-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register > is > + returned. This function must guarantee that all PCI read and write > operations > + are serialized. Extra left bits in OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and > EndBit, then ASSERT(). > + > + @param Address PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..7. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldOr8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 OrData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), StartBit, EndBit, OrData); > +} > + > +/** > + Reads a bit field in an 8-bit PCI configuration register, performs a > bitwise > + AND, and writes the result back to the bit field in the 8-bit register. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, and > + writes the result to the 8-bit PCI configuration register specified by > + Address. The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > + serialized. Extra left bits in AndData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit > and EndBit, then ASSERT(). > + > + @param Address PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..7. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldAnd8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 AndData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), StartBit, EndBit, AndData); > +} MmioBitFieldAnd8 > + > +/** > + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a > + bitwise OR, and writes the result back to the bit field in the 8-bit port. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise AND followed by a bitwise OR between the read result and > + the value specified by AndData, and writes the result to the 8-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all > PCI > + read and write operations are serialized. Extra left bits in both AndData > and > + OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit > and EndBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and > EndBit, then ASSERT(). > + > + @param Address PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..7. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param AndData The value to AND with the PCI configuration register. > + @param OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldAndThenOr8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 AndData, > + IN UINT8 OrData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldAndThenOr8 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit, AndData, OrData); > +} > + > +/** > + Reads a 16-bit PCI configuration register. > + > + Reads and returns the 16-bit PCI configuration register specified by > Address. > + This function must guarantee that all PCI read and write operations are > serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + > + @return The 16-bit PCI configuration register specified by Address. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentRead16 ( > + IN UINT64 Address > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count)); > +} > + > +/** > + Writes a 16-bit PCI configuration register. > + > + Writes the 16-bit PCI configuration register specified by Address with the > value specified by Value. > + Value is returned. This function must guarantee that all PCI read and > write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param Value The value to write. > + > + @return The parameter of Value. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentWrite16 ( > + IN UINT64 Address, > + IN UINT16 Value > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), Value); > +} > + > +/** > + Performs a bitwise OR of a 16-bit PCI configuration register with > + a 16-bit value. > + > + Reads the 16-bit PCI configuration register specified by Address, performs > a > + bitwise OR between the read result and the value specified by OrData, and > + writes the result to the 16-bit PCI configuration register specified by > Address. > + The value written to the PCI configuration register is returned. This > function > + must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function and > + Register. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentOr16 ( > + IN UINT64 Address, > + IN UINT16 OrData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), OrData); > +} > + > +/** > + Performs a bitwise AND of a 16-bit PCI configuration register with a > 16-bit value. > + > + Reads the 16-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by > AndData, > + and writes the result to the 16-bit PCI configuration register specified > by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentAnd16 ( > + IN UINT64 Address, > + IN UINT16 AndData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioAnd16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), AndData); > +} > + > +/** > + Performs a bitwise AND of a 16-bit PCI configuration register with a > 16-bit value, > + followed a bitwise OR with another 16-bit value. > + > + Reads the 16-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by > AndData, > + performs a bitwise OR between the result of the AND operation and the > value specified by OrData, > + and writes the result to the 16-bit PCI configuration register specified > by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param AndData The value to AND with the PCI configuration register. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentAndThenOr16 ( > + IN UINT64 Address, > + IN UINT16 AndData, > + IN UINT16 OrData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), AndData, OrData); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in a 16-bit PCI configuration register. The bit field > is > + specified by the StartBit and the EndBit. The value of the bit field is > + returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param Address PCI configuration register to read. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..15. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + > + @return The value of the bit field read from the PCI configuration > register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldRead16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldRead16 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 16-bit register is returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If Value is larger than the bitmask value range specified by StartBit and > EndBit, then ASSERT(). > + > + @param Address PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..15. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + @param Value New value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldWrite16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 Value > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldWrite16 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit, Value); > +} > + > +/** > + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, > writes > + the result back to the bit field in the 16-bit port. > + > + Reads the 16-bit PCI configuration register specified by Address, performs > a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 16-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register > is > + returned. This function must guarantee that all PCI read and write > operations > + are serialized. Extra left bits in OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and > EndBit, then ASSERT(). > + > + @param Address PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..15. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldOr16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 OrData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldOr16 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit, OrData); > +} > + > +/** > + Reads a bit field in a 16-bit PCI configuration register, performs a > bitwise > + AND, writes the result back to the bit field in the 16-bit register. > + > + Reads the 16-bit PCI configuration register specified by Address, performs > a > + bitwise AND between the read result and the value specified by AndData, and > + writes the result to the 16-bit PCI configuration register specified by > + Address. The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > + serialized. Extra left bits in AndData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit > and EndBit, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..15. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldAnd16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 AndData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldOr16 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit, AndData); > +} MmioBitFieldAnd16 > + > +/** > + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a > + bitwise OR, and writes the result back to the bit field in the > + 16-bit port. > + > + Reads the 16-bit PCI configuration register specified by Address, performs > a > + bitwise AND followed by a bitwise OR between the read result and > + the value specified by AndData, and writes the result to the 16-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all > PCI > + read and write operations are serialized. Extra left bits in both AndData > and > + OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit > and EndBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and > EndBit, then ASSERT(). > + > + @param Address PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..15. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + @param AndData The value to AND with the PCI configuration register. > + @param OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldAndThenOr16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 AndData, > + IN UINT16 OrData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldAndThenOr16 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit, AndData, OrData); > +} > + > +/** > + Reads a 32-bit PCI configuration register. > + > + Reads and returns the 32-bit PCI configuration register specified by > Address. > + This function must guarantee that all PCI read and write operations are > serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + > + @return The 32-bit PCI configuration register specified by Address. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentRead32 ( > + IN UINT64 Address > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count)); > +} > + > +/** > + Writes a 32-bit PCI configuration register. > + > + Writes the 32-bit PCI configuration register specified by Address with the > value specified by Value. > + Value is returned. This function must guarantee that all PCI read and > write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param Value The value to write. > + > + @return The parameter of Value. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentWrite32 ( > + IN UINT64 Address, > + IN UINT32 Value > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), Value); > +} > + > +/** > + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit > value. > + > + Reads the 32-bit PCI configuration register specified by Address, > + performs a bitwise OR between the read result and the value specified by > OrData, > + and writes the result to the 32-bit PCI configuration register specified > by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentOr32 ( > + IN UINT64 Address, > + IN UINT32 OrData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), OrData); > +} > + > +/** > + Performs a bitwise AND of a 32-bit PCI configuration register with a > 32-bit value. > + > + Reads the 32-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by > AndData, > + and writes the result to the 32-bit PCI configuration register specified > by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentAnd32 ( > + IN UINT64 Address, > + IN UINT32 AndData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioAnd32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), AndData); > +} > + > +/** > + Performs a bitwise AND of a 32-bit PCI configuration register with a > 32-bit value, > + followed a bitwise OR with another 32-bit value. > + > + Reads the 32-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by > AndData, > + performs a bitwise OR between the result of the AND operation and the > value specified by OrData, > + and writes the result to the 32-bit PCI configuration register specified > by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param AndData The value to AND with the PCI configuration register. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentAndThenOr32 ( > + IN UINT64 Address, > + IN UINT32 AndData, > + IN UINT32 OrData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, > Count), AndData, OrData); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in a 32-bit PCI configuration register. The bit field > is > + specified by the StartBit and the EndBit. The value of the bit field is > + returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param Address PCI configuration register to read. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..31. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + > + @return The value of the bit field read from the PCI configuration > register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldRead32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldRead32 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 32-bit register is returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If Value is larger than the bitmask value range specified by StartBit and > EndBit, then ASSERT(). > + > + @param Address PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..31. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + @param Value New value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldWrite32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 Value > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldWrite32 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit, Value); > +} > + > +/** > + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and > + writes the result back to the bit field in the 32-bit port. > + > + Reads the 32-bit PCI configuration register specified by Address, performs > a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 32-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register > is > + returned. This function must guarantee that all PCI read and write > operations > + are serialized. Extra left bits in OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and > EndBit, then ASSERT(). > + > + @param Address PCI configuration register to write. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..31. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + @param OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldOr32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 OrData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldOr32 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit, OrData); > +} > + > +/** > + Reads a bit field in a 32-bit PCI configuration register, performs a > bitwise > + AND, and writes the result back to the bit field in the 32-bit register. > + > + > + Reads the 32-bit PCI configuration register specified by Address, performs > a bitwise > + AND between the read result and the value specified by AndData, and writes > the result > + to the 32-bit PCI configuration register specified by Address. The value > written to > + the PCI configuration register is returned. This function must guarantee > that all PCI > + read and write operations are serialized. Extra left bits in AndData are > stripped. > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit > and EndBit, then ASSERT(). > + > + @param Address Address that encodes the PCI Segment, Bus, Device, > Function, and Register. > + @param StartBit The ordinal of the least significant bit in the bit > field. > + Range 0..31. > + @param EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + @param AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldAnd32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 AndData > + ) > +{ > + UINTN Count; > + PCI_SEGMENT_INFO *SegmentInfo; > + > + SegmentInfo = GetPciSegmentInfo (&Count); > + return MmioBitFieldOr32 (PciSegmentLibGetEcamAddress (Address, > SegmentInfo, Count), StartBit, EndBit, AndData); > +} MmioBitFieldAnd32 -- Ard. _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
