On Wed, Nov 29, 2017 at 06:44:59PM +0000, Ard Biesheuvel wrote: > As it turns out, getting the PCIe controllers to switch to Gen2 speed > is surprisingly easy. It only involves setting the 'speed change' bit > in the controller at initialization time, after which the hardware > will automatically attempt to switch to Gen2 speed after training at > Gen1 speed has completed. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel <[email protected]>
Hmm? Well, that sounds like an improvement. Reviewed-by: Leif Lindholm <[email protected]> > --- > > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git > a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > > b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > index 6b42d3e29806..e63b3a4bb23b 100644 > --- > a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > +++ > b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > @@ -113,6 +113,9 @@ > #define PROGRAM_INTERFACE 0x0000FF00 > #define PROGRAM_INTERFACE_VALUE 0x00 > > +#define GEN2_CONTROL_OFF 0x80c > +#define DIRECT_SPEED_CHANGE BIT17 > + > #define MISC_CONTROL_1_OFF 0x8BC > #define DBI_RO_WR_EN BIT0 > > @@ -295,6 +298,9 @@ PciInitController ( > EFI_PCI_COMMAND_MEMORY_SPACE | > EFI_PCI_COMMAND_BUS_MASTER); > > + // Force link speed change to Gen2 at link up > + MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE); > + > // Region 0: MMIO32 range > ConfigureWindow (DbiBase, 0, > RootBridge->Mem.Base, > -- > 2.11.0 > _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
