From: Wasim Khan <[email protected]> Library to provide functions for accessing FPGA on LS2088ARDB board.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wasim Khan <[email protected]> --- .../NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h | 166 +++++++++++++++++++++ .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c | 115 ++++++++++++++ .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 ++++ 3 files changed, 312 insertions(+) create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf diff --git a/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h new file mode 100644 index 0000000..84d1f02 --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h @@ -0,0 +1,166 @@ +/** FpgaLib.h +* Header defining the LS2088a Fpga specific constants (Base addresses, sizes, flags) +* +* Copyright 2017-2018 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __LS2088A_FPGA_H__ +#define __LS2088A_FPGA_H__ + +typedef enum { + CLK_66, + CLK_83, + CLK_100, + CLK_125, + CLK_133 +} SYSTEM_CLOCK; + +/* + * FPGA register set of LS2088ARDB board-specific. + */ +typedef struct { + UINT8 Id; // ID value uniquely identifying each QorIQ board type + UINT8 Arch; // Board Version + UINT8 Ver; // FPGA Version + UINT8 Model; // Programming Model + UINT8 Minor; // Minor Revision Number + UINT8 CtlSys; + UINT8 Aux; + UINT8 ClkSpd; + UINT8 StatDut; + UINT8 StatSys; + UINT8 StatAlrm; + UINT8 Present; + UINT8 Present2; + UINT8 RcwCtl; + UINT8 CtlLed; + UINT8 I2cBlk; + UINT8 RcfgCtl; + UINT8 RcfgSt; + UINT8 DcmAd; + UINT8 DcmDa; + UINT8 Dcmd; + UINT8 Dmsg; + UINT8 Gdc; + UINT8 Gdd; + UINT8 Dmack; + UINT8 Res1[6]; + UINT8 Watch; + UINT8 PwrCtl[2]; + UINT8 Res2[2]; + UINT8 PwrStat[4]; + UINT8 Res3[8]; + UINT8 ClkSpd2[2]; + UINT8 Res4[2]; + UINT8 Sclk[3]; + UINT8 Res5; + UINT8 Dclk[3]; + UINT8 Res6; + UINT8 ClkDspd[3]; + UINT8 Res7; + UINT8 RstCtl; + UINT8 RstStat; + UINT8 RstRsn; + UINT8 RstFrc[2]; + UINT8 Res8[11]; + UINT8 BrdCfg[16]; + UINT8 DutCfg[16]; + UINT8 RcwAd[2]; + UINT8 RcwData; + UINT8 Res9[5]; + UINT8 PostCtl; + UINT8 PostStat; + UINT8 PostDat[2]; + UINT8 Pid[4]; + UINT8 GpioIo[4]; + UINT8 GpioDir[4]; + UINT8 Res10[20]; + UINT8 RjtagCtl; + UINT8 RjtagDat; + UINT8 Res11[2]; + UINT8 TrigSrc[4]; + UINT8 TrigDst[4]; + UINT8 TrigStat; + UINT8 Res12[3]; + UINT8 TrigCtr[4]; + UINT8 Res13[16]; + UINT8 ClkFreq[6]; + UINT8 ResC6[8]; + UINT8 ClkBase[2]; + UINT8 ResD0[8]; + UINT8 Cms[2]; + UINT8 ResC0[6]; + UINT8 Aux2[4]; + UINT8 Res14[10]; + UINT8 AuxAd; + UINT8 AuxDa; + UINT8 Res15[16]; +} FPGA_REG_SET; + +/** + Function to read FPGA register. +**/ +UINT8 +FpgaRead ( + UINTN Reg + ); + +/** + Function to write FPGA register. +**/ +VOID +FpgaWrite ( + UINTN Reg, + UINT8 Value + ); + +/** + Function to initialize FPGA timings. +**/ +VOID +FpgaInit ( + VOID + ); + +/** + Function to get system clock frequency. +**/ +UINTN +GetBoardSysClk ( + VOID + ); + +/** + Function to print board personality. +**/ +VOID +PrintBoardPersonality ( + VOID + ); + +#define FPGA_BASE_PHYS 0x520000000 + +//SYSCLK +#define FPGA_CLK_MASK 0x0F // FPGA Clock Mask +#define SYSCLK_66_MHZ 66000000 +#define SYSCLK_83_MHZ 83000000 +#define SYSCLK_100_MHZ 100000000 +#define SYSCLK_125_MHZ 125000000 +#define SYSCLK_133_MHZ 133000000 + +#define FPGA_VBANK_MASK 0x07 +#define FPGA_CS_MASK 0x08 + +#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg)) +#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value) + +#endif // __LS2088A_FPGA_H__ diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c new file mode 100644 index 0000000..8948c21 --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c @@ -0,0 +1,115 @@ +/** @FpgaLib.c + Fpga Library for LS2088A-RDB board, containing functions to + program and read the Fpga registers. + + FPGA is connected to IFC Controller and so MMIO APIs are used + to read/write FPGA registers + + Copyright 2017-2018 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/FpgaLib.h> +#include <Library/IoLib.h> + +/** + Function to read FPGA register. + + @param Reg Register offset of FPGA to read. + +**/ +UINT8 +FpgaRead ( + IN UINTN Reg + ) +{ + VOID *Base; + + Base = (VOID *)FPGA_BASE_PHYS; + + return MmioRead8 ((UINTN)(Base + Reg)); +} + +/** + Function to write FPGA register. + + @param Reg Register offset of FPGA to write. + @param Value Value to be written. + +**/ +VOID +FpgaWrite ( + IN UINTN Reg, + IN UINT8 Value + ) +{ + VOID *Base; + + Base = (VOID *)FPGA_BASE_PHYS; + + MmioWrite8 ((UINTN)(Base + Reg), Value); +} + +/** + Function to get board system clock frequency. + +**/ +UINTN +GetBoardSysClk ( + VOID + ) +{ + UINT8 SysclkConf; + SysclkConf = FPGA_READ (BrdCfg[1]); + switch (SysclkConf & FPGA_CLK_MASK) { + case CLK_66: + return SYSCLK_66_MHZ; + case CLK_83: + return SYSCLK_83_MHZ; + case CLK_100: + return SYSCLK_100_MHZ; + case CLK_125: + return SYSCLK_125_MHZ; + case CLK_133: + return SYSCLK_133_MHZ; + } + return SYSCLK_100_MHZ; +} + +/** + Function to print board personality. + +**/ +VOID +PrintBoardPersonality ( + VOID + ) +{ + UINT8 SwitchConf; + SwitchConf = FPGA_READ (Arch); + + DEBUG ((DEBUG_INFO, "Board Arch: V%d, ", SwitchConf >> 4)); + DEBUG ((DEBUG_INFO, "Board version: %c, boot from ", + (SwitchConf & 0xf) + 'A')); + + SwitchConf = FPGA_READ (BrdCfg[0]); + + if (SwitchConf & FPGA_CS_MASK) + DEBUG ((DEBUG_INFO, "NAND\n")); + else + DEBUG ((DEBUG_INFO, "vBank: %d\n", (SwitchConf & FPGA_VBANK_MASK))); + + DEBUG ((DEBUG_INFO, "FPGA: v%d.%d\n", FPGA_READ (Ver), + FPGA_READ (Minor))); +} diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf new file mode 100644 index 0000000..e70723a --- /dev/null +++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf @@ -0,0 +1,31 @@ +# @FpgaLib.inf +# +# Copyright 2017-2018 NXP +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x0001000A + BASE_NAME = FpgaLib + FILE_GUID = dd2ce2f3-f219-4b57-82fd-f1ff8ae8bf5a + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = FpgaLib + +[Sources.common] + FpgaLib.c + +[Packages] + MdePkg/MdePkg.dec + Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec + Silicon/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BaseLib + IoLib -- 1.9.1 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
