On 18 February 2018 at 11:39, Leif Lindholm <leif.lindh...@linaro.org> wrote:
> On Fri, Feb 16, 2018 at 06:34:30PM +0000, Ard Biesheuvel wrote:
>> On 16 February 2018 at 17:00, Leif Lindholm <leif.lindh...@linaro.org> wrote:
>> > On Thu, Feb 15, 2018 at 05:20:50PM +0000, Ard Biesheuvel wrote:
>> >> Add a node for the SPI controller to the device tree so the OS may
>> >> attach to it. This is the SPI controller that is attached to the
>> >> 96boards mezzanine connector on Developer Box.
>> > Just a generic question (which also applies to the subsequent patch):
>> > Are there any implications here with regards to this bus running in
>> > master or slave mode?
>> Not really, since that depends entirely on the OS. We just assert the
>> presence of a certain IP block at a certain memory offset, and whether
>> the hardware supports slave mode is left unspecified. Whether the OS
>> supports slave mode (for this particular IP block) is not a property
>> of the hardware.
> I was thinking more along the lines of whether the hardware supports
> slave mode or not (perhaps as a synthesis option).
> But, fair enough.
> If you change SynQuaver -> SynQuacer in 1-2 subject lines, for the series:
> Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
Excellent, thanks. However, I am going to respin this and make it much
- create a separate, generic MezzanineDxe driver (with its own HII menu option)
- redefine all GPIO, I2C and SPI references in terms of the 96boards
spec, e.g., GPIO-A, GPIO-B, GPIO-C
That way, you can basically specify how the LS connector has been
integrated (which I2C/SPI/GPIO), and support anything that the generic
This is only up to a point, of course. Using the Secure96 RNG in UEFI
requires a UEFI driver, and some I2C plumbing, but I am trying to make
that generic as well (which is feasible if the I2C bus on the LS
connector does not contain anything else that UEFI cares about)
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