Good day, Please consider for compatibility with some toolchains, byte-packed structs and unions must be decorated with the define 'PACKED'.
Thanks, Marvin. > -----Original Message----- > From: edk2-devel <edk2-devel-boun...@lists.01.org> On Behalf Of Felix > Polyudov > Sent: Tuesday, February 27, 2018 10:07 PM > To: edk2-devel@lists.01.org > Cc: michael.d.kin...@intel.com; manickavasak...@ami.com; > liming....@intel.com > Subject: [edk2] [Patch v2] MdePkg/Include/IndustryStandard: Add PCI > Express 4.0 header file > > v2: The structure is updated to include all the fields defined in the PCI-E > specification. > > The header includes Physical Layer PCI Express Extended Capability > definitions described in section 7.7.5 of PCI Express Base Specification rev. > 4.0. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Felix Polyudov <fel...@ami.com> > --- > MdePkg/Include/IndustryStandard/PciExpress40.h | 89 > ++++++++++++++++++++++++++ > 1 file changed, 89 insertions(+) > create mode 100644 MdePkg/Include/IndustryStandard/PciExpress40.h > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h > b/MdePkg/Include/IndustryStandard/PciExpress40.h > new file mode 100644 > index 0000000..a832259 > --- /dev/null > +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h > @@ -0,0 +1,89 @@ > +/** @file > +Support for the PCI Express 4.0 standard. > + > +This header file may not define all structures. Please extend as required. > + > +Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR> > +This program and the accompanying materials are licensed and made > +available under the terms and conditions of the BSD License which > +accompanies this distribution. The full text of the license may be > +found at http://opensource.org/licenses/bsd-license.php > + > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > + > +**/ > + > +#ifndef _PCIEXPRESS40_H_ > +#define _PCIEXPRESS40_H_ > + > +#include <IndustryStandard/PciExpress31.h> > + > +#pragma pack(1) > + > +/// The Physical Layer PCI Express Extended Capability definitions. > +/// > +/// Based on section 7.7.5 of PCI Express Base Specification 4.0. > +///@{ > +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID > 0x0026 > +#define > PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1 > + > +// Register offsets from Physical Layer PCI-E Ext Cap Header > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET > 0x04 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET > 0x08 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET > 0x0C > +#define > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_ > OFFSET 0x10 > +#define > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_ > STATUS_OFFSET 0x14 > +#define > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARIT > Y_STATUS_OFFSET 0x18 > +#define > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL > _OFFSET 0x20 > + > +typedef union { > + struct { > + UINT32 Reserved : 32; // Reserved bit 0:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES; > + > +typedef union { > + struct { > + UINT32 Reserved : 32; // Reserved bit 0:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL; > + > +typedef union { > + struct { > + UINT32 EqualizationComplete : 1; // bit 0 > + UINT32 EqualizationPhase1Success : 1; // bit 1 > + UINT32 EqualizationPhase2Success : 1; // bit 2 > + UINT32 EqualizationPhase3Success : 1; // bit 3 > + UINT32 LinkEqualizationRequest : 1; // bit 4 > + UINT32 Reserved : 27; // Reserved bit 5:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS; > + > +typedef union { > + struct { > + UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3 > + UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7 > + } Bits; > + UINT8 Uint8; > +} > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL > ; > + > +typedef struct { > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES > Capablities; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status; > + UINT32 > LocalDataParityMismatchStatus; > + UINT32 > FirstRetimerDataParityMismatchStatus; > + UINT32 > SecondRetimerDataParityMismatchStatus; > + UINT32 Reserved; > + > PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL > +LaneEqualizationControl; } > +PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0; > +///@} > + > +#pragma pack() > + > +#endif > -- > 2.10.0.windows.1 > > > > Please consider the environment before printing this email. > > The information contained in this message may be confidential and > proprietary to American Megatrends, Inc. This communication is intended to > be read only by the individual or entity to whom it is addressed or by their > designee. If the reader of this message is not the intended recipient, you are > on notice that any distribution of this message, in any form, is strictly > prohibited. Please promptly notify the sender by reply e-mail or by > telephone at 770-246-8600, and then delete or destroy all copies of the > transmission. > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
