If timer interrupt is level sensitive, reloading timer compare
register has a side effect of clearing GIC pending status, so a "ISB"
is needed to make sure this instruction is executed before enabling
CPU IRQ, or else we may get spurious timer interrupts.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi....@linaro.org>
Signed-off-by: Yi Li <phoenix.l...@huawei.com>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.com>
---
Notes:
v2:
- Use ISB instead of DSB [Marc]
- Update commit message accordingly.
ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c
b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
index 33d7c922221f..32abee8726a0 100644
--- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c
+++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
@@ -337,6 +337,7 @@ TimerInterruptHandler (
// Set next compare value
ArmGenericTimerSetCompareVal (CompareValue);
+ ArmInstructionSynchronizationBarrier ();
ArmGenericTimerEnableTimer ();
}
--
2.7.4
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