Rename the variable to "gPatchSmmCr3" so that its association with PatchInstructionX86() is clear from the declaration, change its type to X86_ASSEMBLY_PATCH_LABEL, and patch it with PatchInstructionX86(). This lets us remove the binary (DB) encoding of some instructions in "SmmInit.nasm".
Cc: Eric Dong <[email protected]> Cc: Michael D Kinney <[email protected]> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <[email protected]> --- Notes: v2: - use the X86_ASSEMBLY_PATCH_LABEL type rather than UINT8 [Mike] UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 2 +- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 6 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm | 6 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index a2babb987732..31633498e178 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -309,7 +309,7 @@ extern IA32_FAR_ADDRESS gSmmJmpAddr; extern CONST UINT8 gcSmmInitTemplate[]; extern CONST UINT16 gcSmmInitSize; extern UINT32 gSmmCr0; -extern UINT32 gSmmCr3; +X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3; extern UINT32 gSmmCr4; extern UINTN gSmmInitStack; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm index d64fcd48d03e..f7bb9b9a82e5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm @@ -22,7 +22,7 @@ extern ASM_PFX(SmmInitHandler) extern ASM_PFX(mRebasedFlag) extern ASM_PFX(mSmmRelocationOriginalAddress) -global ASM_PFX(gSmmCr3) +global ASM_PFX(gPatchSmmCr3) global ASM_PFX(gSmmCr4) global ASM_PFX(gSmmCr0) global ASM_PFX(gSmmJmpAddr) @@ -49,8 +49,8 @@ ASM_PFX(SmmStartup): mov ebx, edx ; rdmsr will change edx. keep it in ebx. and ebx, BIT20 ; extract NX capability bit shr ebx, 9 ; shift bit to IA32_EFER.NXE[BIT11] position - DB 0x66, 0xb8 ; mov eax, imm32 -ASM_PFX(gSmmCr3): DD 0 + mov eax, strict dword 0 ; source operand will be patched +ASM_PFX(gPatchSmmCr3): mov cr3, eax o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))] DB 0x66, 0xb8 ; mov eax, imm32 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm index 2eaf1433dcd6..2df22a1f6cd1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm @@ -22,7 +22,7 @@ extern ASM_PFX(SmmInitHandler) extern ASM_PFX(mRebasedFlag) extern ASM_PFX(mSmmRelocationOriginalAddress) -global ASM_PFX(gSmmCr3) +global ASM_PFX(gPatchSmmCr3) global ASM_PFX(gSmmCr4) global ASM_PFX(gSmmCr0) global ASM_PFX(gSmmJmpAddr) @@ -47,8 +47,8 @@ ASM_PFX(SmmStartup): mov eax, 0x80000001 ; read capability cpuid mov ebx, edx ; rdmsr will change edx. keep it in ebx. - DB 0x66, 0xb8 ; mov eax, imm32 -ASM_PFX(gSmmCr3): DD 0 + mov eax, strict dword 0 ; source operand will be patched +ASM_PFX(gPatchSmmCr3): mov cr3, eax o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))] DB 0x66, 0xb8 ; mov eax, imm32 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index a27d1f4684f5..c5b67e3dc0ce 100755 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -406,7 +406,7 @@ SmmRelocateBases ( // Patch ASM code template with current CR0, CR3, and CR4 values // gSmmCr0 = (UINT32)AsmReadCr0 (); - gSmmCr3 = (UINT32)AsmReadCr3 (); + PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4); gSmmCr4 = (UINT32)AsmReadCr4 (); // -- 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
