Hi, (CC Marcel)
On 04/02/18 08:55, Tiger Liu(BJ-RD) wrote: > Hi, Laszlo: > I have a question you would like to ask you. > Could I study pcie native hot plug feature with ovmf? > > It seems qemu emulates Q35 chipset. > And ovmf provides PciHotPlugInitDxe driver. Sure. Here's some tips I can give you: * The first PCI Express -- not traditional PCI -- hotplug feature request for OVMF arrived in <https://github.com/tianocore/edk2/issues/32>. That link is dead now, because we abandoned the GitHub issue tracker. Instead, the report was migrated to <https://bugzilla.tianocore.org/show_bug.cgi?id=75>. This issue got solved by adding MMCONFIG (ECAM) config space access to OVMF. Without MMCONFIG, PCIe hotplug in the guest OS would not work. Please see Marcel's analysis in the TianoCore BZ linked above. The edk2 commit range is noted in comment 32. * Once config space access works like that, you need the PCIe enumeration / resource assignment (which occurs in the firmware) to account for PCI resources *in advance* that hotplugged endpoints *might* require. This means reserving various kinds of apertures. On the QEMU side, this is documented in the following two text files (in the QEMU tree): - docs/pcie.txt - docs/pcie_pci_bridge.txt In particular there is a "resource reservation hint" PCIe capability (for PCIe root ports) that QEMU can populate and OVMF can parse. Then OVMF informs PciBusDxe to reserve the appropriate resources. * PCI_HOT_PLUG_INIT_PROTOCOL (implemented in OVMF by OvmfPkg/PciHotPlugInitDxe) is defined by the PI spec. Roughly, it has two purposes: it can (a) report+initialize non-enumerable [*] hotplug controllers (of which QEMU has none) to PciBusDxe, (b) it can convey reservation hints ("resource paddings") to PciBusDxe. OVMF stubs out the two interfaces related to purpose (a), and implements the GetResourcePadding() member function (purpose (b)) by translating QEMU's PCIe capability to the format expected by the PI spec and PciBusDxe. [*] The PI spec calls this kind of hotplug controller "root" HPC, but that has nothing to do with "root" in the PCIe sense. In this terminology, "root HPC" simply means "non-enumerable", and "non-root HPC" means "enumerable" through the normal PCI(e) traversal. Hope this helps, Laszlo _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
