A few style comments in addition to the requested layout changes.
On Fri, Feb 16, 2018 at 02:20:20PM +0530, Meenakshi wrote:
> From: Wasim Khan <[email protected]>
>
> Added SocInit function that initializes peripherals
> and print board and soc information for LS2088ARDB Board.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <[email protected]>
> ---
> Silicon/NXP/Chassis/Chassis.c | 35 ++++++
> Silicon/NXP/Chassis/Chassis.h | 17 +++
> Silicon/NXP/Chassis/Chassis3/Chassis3.dec | 19 ++++
> Silicon/NXP/Chassis/Chassis3/SerDes.h | 91 +++++++++++++++
> Silicon/NXP/Chassis/Chassis3/Soc.c | 180
> ++++++++++++++++++++++++++++++
> Silicon/NXP/Chassis/Chassis3/Soc.h | 150 +++++++++++++++++++++++++
> Silicon/NXP/Chassis/LS2088aSocLib.inf | 48 ++++++++
> Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 +++++++++++
> 8 files changed, 607 insertions(+)
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> create mode 100644 Silicon/NXP/Chassis/Chassis3/SerDes.h
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.c
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.h
> create mode 100644 Silicon/NXP/Chassis/LS2088aSocLib.inf
> create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
>
> diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
> index ce07fdc..b63efdc 100644
> --- a/Silicon/NXP/Chassis/Chassis.c
> +++ b/Silicon/NXP/Chassis/Chassis.c
> @@ -45,6 +45,7 @@ GurRead (
> STATIC CPU_TYPE CpuTypeList[] = {
> CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
> + CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
> };
>
> /*
> @@ -142,6 +143,40 @@ CpuNumCores (
> }
>
> /*
> + * Return core's cluster
> + */
> +UINT32
> +QoriqCoreToCluster (
> + IN UINTN Core
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER;
> InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (Count == Core)
Always {} with if.
> + return ClusterIndex;
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return -1; // cannot identify the cluster
> +}
> +
> +/*
> * Return the type of core i.e. A53, A57 etc of inputted
> * core number.
> */
> diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
> index 0beb44c..974fefb 100644
> --- a/Silicon/NXP/Chassis/Chassis.h
> +++ b/Silicon/NXP/Chassis/Chassis.h
> @@ -57,6 +57,7 @@ CpuMaskNext (
> #define SVR_WO_E 0xFFFFFE
> #define SVR_LS1043A 0x879200
> #define SVR_LS1046A 0x870700
> +#define SVR_LS2088A 0x870901
>
> #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> #define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> @@ -142,4 +143,20 @@ CpuNumCores (
> VOID
> );
>
> +/*
> + * Return the type of initiator for core/hardware accelerator for given core
> index.
> + */
> +UINT32
> +QoriqCoreToType (
> + IN UINTN Core
> + );
> +
> +/*
> + * Return the cluster of initiator for core/hardware accelerator for given
> core index.
> + */
> +UINT32
> +QoriqCoreToCluster (
> + IN UINTN Core
> + );
> +
> #endif /* __CHASSIS_H__ */
> diff --git a/Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> b/Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> new file mode 100644
> index 0000000..cf41b3c
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> @@ -0,0 +1,19 @@
> +# @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made
> available under
> +# the terms and conditions of the BSD License which accompanies this
> distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
0x0001001a
> +
> +[Includes]
> + .
> diff --git a/Silicon/NXP/Chassis/Chassis3/SerDes.h
> b/Silicon/NXP/Chassis/Chassis3/SerDes.h
> new file mode 100644
> index 0000000..a77ddd5
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis3/SerDes.h
> @@ -0,0 +1,91 @@
> +/** SerDes.h
> + The Header file of SerDes Module for Chassis 3
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD
> License
> + which accompanies this distribution. The full text of the license may be
> found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +
> +**/
> +
> +#ifndef __SERDES_H__
> +#define __SERDES_H__
> +
> +#include <Uefi/UefiBaseType.h>
> +
> +#define SRDS_MAX_LANES 8
> +
> +//
> +// SerDes lane protocols/devices
> +//
> +typedef enum {
> + NONE = 0,
> + PCIE1,
> + PCIE2,
> + PCIE3,
> + PCIE4,
> + SATA1,
> + SATA2,
> + XAUI1,
> + XAUI2,
> + XFI1,
> + XFI2,
> + XFI3,
> + XFI4,
> + XFI5,
> + XFI6,
> + XFI7,
> + XFI8,
> + SGMII1,
> + SGMII2,
> + SGMII3,
> + SGMII4,
> + SGMII5,
> + SGMII6,
> + SGMII7,
> + SGMII8,
> + SGMII9,
> + SGMII10,
> + SGMII11,
> + SGMII12,
> + SGMII13,
> + SGMII14,
> + SGMII15,
> + SGMII16,
> + QSGMII_A,
> + QSGMII_B,
> + QSGMII_C,
> + QSGMII_D,
> + // Number of entries in this enum
> + SERDES_PRTCL_COUNT
> +} SERDES_PROTOCOL;
> +
> +typedef enum {
> + SRDS_1 = 0,
> + SRDS_2,
> + SRDS_MAX_NUM
> +} SERDES_NUMBER;
> +
> +typedef struct {
> + UINT16 Protocol;
> + UINT8 SrdsLane[SRDS_MAX_LANES];
> +} SERDES_CONFIG;
> +
> +typedef VOID
> +(*SERDES_PROBE_LANES_CALLBACK) (
> + IN SERDES_PROTOCOL LaneProtocol,
> + IN VOID *Arg
> + );
> +
> +VOID
> +SerDesProbeLanes(
> + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> + IN VOID *Arg
> + );
> +
> +#endif /* __SERDES_H */
> diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.c
> b/Silicon/NXP/Chassis/Chassis3/Soc.c
> new file mode 100644
> index 0000000..ed6c3cc
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis3/Soc.c
> @@ -0,0 +1,180 @@
> +/** @Soc.c
> + SoC specific Library containg functions to initialize various SoC
> components
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD
> License
> + which accompanies this distribution. The full text of the license may be
> found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Chassis.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib/MemLibInternals.h>
Please use CopyMem directly instead.
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +#include "Soc.h"
> +
> +VOID
> +GetSysInfo (
> + OUT SYS_INFO *PtrSysInfo
> + )
> +{
> + UINT32 Index;
> + CCSR_GUR *GurBase;
> + CCSR_CLT_CTRL *ClkBase;
> + CCSR_CLK_CLUSTER *ClkGrp[2] = {
> + (VOID *) (FSL_CLK_GRPA_ADDR),
> + (VOID *) (FSL_CLK_GRPB_ADDR)
> + };
> +
> + const UINT8 CoreCplxPll[16] = {
CONST
> + [0] = 0, // CC1 PPL / 1
> + [1] = 0, // CC1 PPL / 2
> + [2] = 0, // CC1 PPL / 4
> + [4] = 1, // CC2 PPL / 1
> + [5] = 1, // CC2 PPL / 2
> + [6] = 1, // CC2 PPL / 4
> + [8] = 2, // CC3 PPL / 1
> + [9] = 2, // CC3 PPL / 2
> + [10] = 2, // CC3 PPL / 4
> + [12] = 3, // CC4 PPL / 1
> + [13] = 3, // CC4 PPL / 2
> + [14] = 3, // CC4 PPL / 4
> + };
> +
> + const UINT8 CoreCplxPllDivisor[16] = {
> + [0] = 1, // CC1 PPL / 1
> + [1] = 2, // CC1 PPL / 2
> + [2] = 4, // CC1 PPL / 4
> + [4] = 1, // CC2 PPL / 1
> + [5] = 2, // CC2 PPL / 2
> + [6] = 4, // CC2 PPL / 4
> + [8] = 1, // CC3 PPL / 1
> + [9] = 2, // CC3 PPL / 2
> + [10] = 4, // CC3 PPL / 4
> + [12] = 1, // CC4 PPL / 1
> + [13] = 2, // CC4 PPL / 2
> + [14] = 4, // CC4 PPL / 4
> + };
> +
> + INT32 CcGroup[12] = FSL_CLUSTER_CLOCKS;
> + UINTN PllCount;
> + UINTN Cluster;
> + UINTN FreqCPll[NUM_CC_PLLS];
> + UINTN PllRatio[NUM_CC_PLLS];
> + UINTN SysClk;
> + UINT32 Cpu;
> + UINT32 CPllSel;
> + UINT32 CplxPll;
> + VOID *Offset;
> +
> + SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> + SysClk = CLK_FREQ;
> +
> + PtrSysInfo->FreqSystemBus = SysClk;
> + PtrSysInfo->FreqDdrBus = PcdGet64 (PcdDdrClk);
> + PtrSysInfo->FreqDdrBus2 = PcdGet64 (PcdDdrClk);
> +
> + //
> + // selects the platform clock:SYSCLK ratio and calculate
> + // system frequency
> + //
> + PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> + CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT) &
> + CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK;
Indent like so?:
PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT) &
CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK;
> +
> + //
> + // Platform clock is half of platform PLL
> + //
> + PtrSysInfo->FreqSystemBus /= PcdGet32 (PcdPlatformFreqDiv);
> +
> + //
> + // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
> + //
> + PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> + CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT) &
> + CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK;
> + PtrSysInfo->FreqDdrBus2 *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> + CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT) &
> + CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK;
Same indentation change above, x2?
> +
> + for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
> + Offset = (VOID *)((UINTN)ClkGrp[PllCount/3] +
> + __builtin_offsetof (CCSR_CLK_CLUSTER, PllnGsr[PllCount%3].Gsr));
> + PllRatio[PllCount] = (GurRead ((UINTN)Offset) >> 1) & 0x3f;
> + FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
> + }
> +
> + //
> + // Calculate Core frequency
> + //
> + ForEachCpu (Index, Cpu, CpuNumCores (), CpuMask ()) {
> + Cluster = QoriqCoreToCluster (Cpu);
> + ASSERT_EFI_ERROR (Cluster);
> + CPllSel = (GurRead ((UINTN)&ClkBase->ClkCnCsr[Cluster].Csr) >> 27) & 0xf;
> + CplxPll = CoreCplxPll[CPllSel];
> + CplxPll += CcGroup[Cluster] - 1;
> + PtrSysInfo->FreqProcessor[Cpu] = FreqCPll[CplxPll] /
> CoreCplxPllDivisor[CPllSel];
> + }
> + PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32
> (PcdPlatformFreqDiv);
> +}
> +
> +/**
> + Perform the early initialization.
> + This function is called by the ArmPlatformPkg/Pei or
> ArmPlatformPkg/Pei/PlatformPeim
> +
> +**/
> +VOID
> +SocInit (
> + VOID
> + )
> +{
> + CHAR8 Buffer[100];
> + UINTN CharCount;
> +
> + //
> + // Initialize SMMU
> + //
> + SmmuInit ();
> +
> + //
> + // Initialize the Serial Port.
> + // Early serial port initialization is required to print RCW, Soc and CPU
> infomation at
> + // the begining of UEFI boot.
> + //
> + SerialPortInitialize ();
> +
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\nUEFI firmware
> (version %s built at %a on %a)\n\r",
Can you move the format string to the line below, indented, to keep
line length down?
> + (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__);
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> +
> + //
> + // Print CPU information
> + //
> + PrintCpuInfo ();
> +
> + //
> + // Print Reset Controll Word
> + //
> + PrintRCW ();
> +
> + //
> + // Print Soc Personality information
> + //
> + PrintSoc ();
> +}
> +
> diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.h
> b/Silicon/NXP/Chassis/Chassis3/Soc.h
> new file mode 100644
> index 0000000..0e892fb
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis3/Soc.h
> @@ -0,0 +1,150 @@
> +/** Soc.h
> +* Header defining the Base addresses, sizes, flags etc for chassis 1
> +*
> +* Copyright (c) 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD
> License
> +* which accompanies this distribution. The full text of the license may be
> found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +*
> +**/
> +
> +#ifndef __SOC_H__
> +#define __SOC_H__
> +
> +#define MAX_CPUS 16
> +#define FSL_CLK_GRPA_ADDR 0x01300000
> +#define FSL_CLK_GRPB_ADDR 0x01310000
> +#define NUM_CC_PLLS 6
> +#define CLK_FREQ 100000000
> +
> +#define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
> +#define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of
> clusters */
> +#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) !=
> TP_CLUSTER_EOC_MASK)
> +
> +// RCW SERDES MACRO
> +#define RCWSR_INDEX 28
> +#define RCWSR_SRDS1_PRTCL_MASK 0x00ff0000
> +#define RCWSR_SRDS1_PRTCL_SHIFT 16
> +#define RCWSR_SRDS2_PRTCL_MASK 0xff000000
> +#define RCWSR_SRDS2_PRTCL_SHIFT 24
> +
> +// SMMU Defintions
> +#define SMMU_BASE_ADDR 0x05000000
> +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> +
> +#define SACR_PAGESIZE_MASK 0x00010000
> +#define SCR0_CLIENTPD_MASK 0x00000001
> +#define SCR0_USFCFG_MASK 0x00000400
> +
> +typedef struct {
> + UINTN FreqProcessor[MAX_CPUS];
> + UINTN FreqSystemBus;
> + UINTN FreqDdrBus;
> + UINTN FreqDdrBus2;
> + UINTN FreqLocalBus;
> + UINTN FreqSdhc;
> + UINTN FreqFman[1];
> + UINTN FreqQman;
> + UINTN FreqPme;
> +}SYS_INFO;
> +
> +///
> +/// Device Configuration and Pin Control
> +///
> +typedef struct {
> + UINT32 PorSr1; // POR status register 1
> + UINT32 PorSr2; // POR status register 2
> + UINT8 Res008[0x20-0x8];
Just a note here: I see what this is doing, it is perfectly legal C,
and I don't see anything in the code style banning it.
But I don't think I've come across it before :)
/
Leif
> + UINT32 GppOrCr1; // General-purpose POR configuration register
> + UINT32 GppOrCr2; // General-purpose POR configuration register 2
> + UINT32 DcfgFuseSr; // Fuse status register */
> + UINT32 GppOrCr3;
> + UINT32 GppOrCr4;
> + UINT8 Res034[0x70-0x34];
> + UINT32 DevDisr; // Device disable control register
> + UINT32 DevDisr2; // Device disable control register 2
> + UINT32 DevDisr3; // Device disable control register 3
> + UINT32 DevDisr4; // Device disable control register 4
> + UINT32 DevDisr5; // Device disable control register 5
> + UINT32 DevDisr6; // Device disable control register 6
> + UINT32 DevDisr7; // Device disable control register 7
> + UINT8 Res08c[0x90-0x8c];
> + UINT32 CoreDisrUpper; // CORE DISR Uppper for support of 64 cores
> + UINT32 CoreDisrLower; // CORE DISR Lower for support of 64 cores
> + UINT8 Res098[0xa0-0x98];
> + UINT32 Pvr; // Processor version
> + UINT32 Svr; // System version
> + UINT32 Mvr; // Manufacturing version
> + UINT8 Res0ac[0x100-0xac];
> + UINT32 RcwSr[32]; // Reset control word status
> +#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT 2
> +#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK 0x1f
> +#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT 10
> +#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK 0x3f
> +#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT 18
> +#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK 0x3f
> + UINT8 Res180[0x200-0x180];
> + UINT32 ScratchRw[32]; // Scratch Read/Write
> + UINT8 Res280[0x300-0x280];
> + UINT32 ScratchW1R[4]; // Scratch Read (Write once)
> + UINT8 Res310[0x400-0x310];
> + UINT32 BootLocPtrL; // Low addr : Boot location pointer
> + UINT32 BootLocPtrH; // High addr : Boot location pointer
> + UINT8 Res408[0x500-0x408];
> + UINT8 Res500[0x740-0x500];
> + UINT32 TpItyp[64];
> + struct {
> + UINT32 Upper;
> + UINT32 Lower;
> + } TpCluster[3];
> + UINT8 Res858[0x1000-0x858];
> +} CCSR_GUR;
> +
> +///
> +/// Clocking
> +///
> +typedef struct {
> + struct {
> + UINT32 Csr; // core cluster n clock control status
> + UINT8 Res04[0x20-0x04];
> + } ClkCnCsr[8];
> +} CCSR_CLT_CTRL;
> +
> +///
> +/// Clock Cluster
> +///
> +typedef struct {
> + struct {
> + UINT8 Res00[0x10];
> + UINT32 Csr; // core cluster n clock control status
> + UINT8 Res14[0x20-0x14];
> + } HwnCsr[3];
> + UINT8 Res60[0x80-0x60];
> + struct {
> + UINT32 Gsr; // core cluster n clock general status
> + UINT8 Res84[0xa0-0x84];
> + } PllnGsr[3];
> + UINT8 Rese0[0x100-0xe0];
> +} CCSR_CLK_CLUSTER;
> +
> +VOID
> +GetSysInfo (
> + OUT SYS_INFO *
> + );
> +
> +UINT32
> +EFIAPI
> +GurRead (
> + IN UINTN Address
> + );
> +
> +#endif /* __SOC_H__ */
> diff --git a/Silicon/NXP/Chassis/LS2088aSocLib.inf
> b/Silicon/NXP/Chassis/LS2088aSocLib.inf
> new file mode 100644
> index 0000000..8a4da50
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/LS2088aSocLib.inf
> @@ -0,0 +1,48 @@
> +# @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD
> License
> +# which accompanies this distribution. The full text of the license may be
> found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = SocLib
> + FILE_GUID = 3b233a6a-0ee1-42a3-a7f7-c285b5ba80dc
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SocLib
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> + Silicon/NXP/LS2088A/LS2088A.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BeIoLib
> + DebugLib
> + SerialPortLib
> +
> +[Sources.common]
> + Chassis.c
> + Chassis3/Soc.c
> + SerDes.c
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk
> diff --git a/Silicon/NXP/LS2088A/Include/SocSerDes.h
> b/Silicon/NXP/LS2088A/Include/SocSerDes.h
> new file mode 100644
> index 0000000..f631ccb
> --- /dev/null
> +++ b/Silicon/NXP/LS2088A/Include/SocSerDes.h
> @@ -0,0 +1,67 @@
> +/** @file
> + The Header file of SerDes Module for LS2088A
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD
> License
> + which accompanies this distribution. The full text of the license may be
> found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +
> +**/
> +
> +#ifndef __SOC_SERDES_H__
> +#define __SOC_SERDES_H__
> +
> +#include <SerDes.h>
> +
> +SERDES_CONFIG SerDes1ConfigTbl[] = {
> + // SerDes 1
> + { 0x03, { PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
> + { 0x05, { PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x07, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 }
> },
> + { 0x09, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 }
> },
> + { 0x0A, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 }
> },
> + { 0x0C, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 }
> },
> + { 0x0E, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 }
> },
> + { 0x26, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
> + { 0x28, { SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
> + { 0x2A, { XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
> + { 0x2B, { SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
> + { 0x32, { XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
> + { 0x33, { PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B,
> QSGMII_A } },
> + { 0x35, { QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
> + {}
> +};
> +
> +SERDES_CONFIG SerDes2ConfigTbl[] = {
> + // SerDes 2
> + { 0x07, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
> SGMII16 } },
> + { 0x09, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
> SGMII16 } },
> + { 0x0A, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
> SGMII16 } },
> + { 0x0C, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
> SGMII16 } },
> + { 0x0E, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
> SGMII16 } },
> + { 0x3D, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
> + { 0x3E, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
> + { 0x3F, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
> + { 0x40, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
> + { 0x41, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
> + { 0x42, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
> + { 0x43, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
> + { 0x44, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
> + { 0x45, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, PCIE4 }
> },
> + { 0x47, { PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
> SGMII16 } },
> + { 0x49, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 }
> },
> + { 0x4A, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 }
> },
> + {}
> +};
> +
> +SERDES_CONFIG *SerDesConfigTbl[] = {
> + SerDes1ConfigTbl,
> + SerDes2ConfigTbl
> +};
> +
> +#endif /* __SOC_SERDES_H */
> --
> 1.9.1
>
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