On Sun, Jun 17, 2018 at 10:11:51PM +0200, Marcin Wojtas wrote:
> This patch introduces new library callbacks for NonDiscoverable devices
> i.e. AHCI/XHCI/SDMMC. They dynamically allocate and fill according
> structures with the SoC description of the devices.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <m...@semihalf.com>
> ---
>
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> | 18 ++++
> Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> | 48 ++++++++++
>
> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> | 92 ++++++++++++++++++++
> 3 files changed, 158 insertions(+)
>
> diff --git
> a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
>
> b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> index d63c3b5..94fd6fa 100644
> ---
> a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> +++
> b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h
> @@ -24,12 +24,24 @@
> #define MV_SOC_CP_BASE(Cp) (0xF2000000 + ((Cp) * 0x2000000))
>
> //
> +// Platform description of AHCI controllers
> +//
> +#define MV_SOC_AHCI_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x540000)
> +#define MV_SOC_AHCI_ID(Cp) ((Cp) % 2)
> +
> +//
> // Platform description of PP2 NIC
> //
> #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE ((Cp))
(It might not hurt with a later patch changing these ((Cp)) to (Cp),
but don't worry about it for this patch. I'm guessing there could be
more than these two instances in this file?)
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
> #define MV_SOC_PP2_CLK_FREQ 333333333
>
> //
> +// Platform description of SDMMC controllers
> +//
> +#define MV_SOC_MAX_SDMMC_COUNT 2
> +#define MV_SOC_SDMMC_BASE(Index) ((Index) == 0 ? 0xF06E0000 :
> 0xF2780000)
> +
> +//
> // Platform description of UTMI PHY's
> //
> #define MV_SOC_UTMI_PER_CP_COUNT 2
> @@ -38,4 +50,10 @@
> #define MV_SOC_UTMI_CFG_BASE 0x440440
> #define MV_SOC_UTMI_USB_CFG_BASE 0x440420
>
> +//
> +// Platform description of XHCI controllers
> +//
> +#define MV_SOC_XHCI_PER_CP_COUNT 2
> +#define MV_SOC_XHCI_BASE(Xhci) (0x500000 + ((Xhci) * 0x10000))
> +
> #endif
> diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> index cafcc0f..3b29d78 100644
> --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> @@ -14,6 +14,54 @@
> #ifndef __ARMADA_SOC_DESC_LIB_H__
> #define __ARMADA_SOC_DESC_LIB_H__
>
> +#include <Library/NonDiscoverableDeviceRegistrationLib.h>
> +
> +//
> +// NonDiscoverable devices SoC description
> +//
> +// AHCI
> +typedef struct {
> + UINTN AhciId;
> + UINTN AhciBaseAddress;
> + UINTN AhciMemSize;
> + NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType;
> +} MV_SOC_AHCI_DESC;
> +
> +EFI_STATUS
> +EFIAPI
> +ArmadaSoCDescAhciGet (
> + IN OUT MV_SOC_AHCI_DESC **AhciDesc,
> + IN OUT UINTN *DescCount
> + );
> +
> +// SDMMC
> +typedef struct {
> + UINTN SdMmcBaseAddress;
> + UINTN SdMmcMemSize;
> + NON_DISCOVERABLE_DEVICE_DMA_TYPE SdMmcDmaType;
> +} MV_SOC_SDMMC_DESC;
> +
> +EFI_STATUS
> +EFIAPI
> +ArmadaSoCDescSdMmcGet (
> + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc,
> + IN OUT UINTN *DescCount
> + );
> +
> +// XHCI
> +typedef struct {
> + UINTN XhciBaseAddress;
> + UINTN XhciMemSize;
> + NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType;
> +} MV_SOC_XHCI_DESC;
> +
> +EFI_STATUS
> +EFIAPI
> +ArmadaSoCDescXhciGet (
> + IN OUT MV_SOC_XHCI_DESC **XhciDesc,
> + IN OUT UINTN *DescCount
> + );
> +
> //
> // PP2 NIC devices SoC description
> //
> diff --git
> a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
>
> b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> index 61b4e30..97fe3f8 100644
> ---
> a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> +++
> b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> @@ -30,6 +30,37 @@
>
> EFI_STATUS
> EFIAPI
> +ArmadaSoCDescAhciGet (
> + IN OUT MV_SOC_AHCI_DESC **AhciDesc,
> + IN OUT UINTN *DescCount
> + )
> +{
> + MV_SOC_AHCI_DESC *Desc;
> + UINTN CpCount, CpIndex;
> +
> + CpCount = FixedPcdGet8 (PcdMaxCpCount);
> +
> + Desc = AllocateZeroPool (CpCount * sizeof (MV_SOC_AHCI_DESC));
> + if (Desc == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
> + Desc[CpIndex].AhciId = MV_SOC_AHCI_ID (CpIndex);
> + Desc[CpIndex].AhciBaseAddress = MV_SOC_AHCI_BASE (CpIndex);
> + Desc[CpIndex].AhciMemSize = SIZE_8KB;
> + Desc[CpIndex].AhciDmaType = NonDiscoverableDeviceDmaTypeCoherent;
> + }
> +
> + *AhciDesc = Desc;
> + *DescCount = CpCount;
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> ArmadaSoCDescPp2Get (
> IN OUT MV_SOC_PP2_DESC **Pp2Desc,
> IN OUT UINTN *DescCount
> @@ -59,6 +90,34 @@ ArmadaSoCDescPp2Get (
>
> EFI_STATUS
> EFIAPI
> +ArmadaSoCDescSdMmcGet (
> + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc,
> + IN OUT UINTN *DescCount
> + )
> +{
> + MV_SOC_SDMMC_DESC *Desc;
> + UINTN Index;
> +
> + Desc = AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof
> (MV_SOC_SDMMC_DESC));
> + if (Desc == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + for (Index = 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) {
> + Desc[Index].SdMmcBaseAddress = MV_SOC_SDMMC_BASE (Index);
> + Desc[Index].SdMmcMemSize = SIZE_1KB;
> + Desc[Index].SdMmcDmaType = NonDiscoverableDeviceDmaTypeCoherent;
> + }
> +
> + *SdMmcDesc = Desc;
> + *DescCount = MV_SOC_MAX_SDMMC_COUNT;
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> ArmadaSoCDescUtmiGet (
> IN OUT MV_SOC_UTMI_DESC **UtmiDesc,
> IN OUT UINTN *DescCount
> @@ -92,3 +151,36 @@ ArmadaSoCDescUtmiGet (
>
> return EFI_SUCCESS;
> }
> +
> +EFI_STATUS
> +EFIAPI
> +ArmadaSoCDescXhciGet (
> + IN OUT MV_SOC_XHCI_DESC **XhciDesc,
> + IN OUT UINTN *DescCount
> + )
> +{
> + MV_SOC_XHCI_DESC *Desc;
> + UINTN CpCount, CpIndex, Index;
> +
> + CpCount = FixedPcdGet8 (PcdMaxCpCount);
> +
> + *DescCount = CpCount * MV_SOC_XHCI_PER_CP_COUNT;
> + Desc = AllocateZeroPool (*DescCount * sizeof (MV_SOC_XHCI_DESC));
> + if (Desc == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + *XhciDesc = Desc;
> +
> + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
> + for (Index = 0; Index < MV_SOC_XHCI_PER_CP_COUNT; Index++) {
> + Desc->XhciBaseAddress = MV_SOC_CP_BASE (CpIndex) + MV_SOC_XHCI_BASE
> (Index);
> + Desc->XhciMemSize = SIZE_16KB;
> + Desc->XhciDmaType = NonDiscoverableDeviceDmaTypeCoherent;
> + Desc++;
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> --
> 2.7.4
>
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