From: Grzegorz Jaszczyk <[email protected]> Replace the comphy initialization for USB with appropriate SMC call, so the ARM-TF will execute required serdes configuration.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <[email protected]> --- Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 167 +------------------- 1 file changed, 4 insertions(+), 163 deletions(-) diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c index c46cad1..35ac459 100755 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -100,168 +100,6 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = { STATIC VOID -ComPhyUsb3RFUConfiguration ( - IN EFI_PHYSICAL_ADDRESS ComPhyAddr -) -{ - UINT32 Mask, Data; - - /* RFU configurations - hard reset ComPhy */ - Mask = COMMON_PHY_CFG1_PWR_UP_MASK; - Data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - Mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; - Data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - Mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - Data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - Data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - Mask |= COMMON_PHY_PHY_MODE_MASK; - Data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); - - /* Release from hard reset */ - Mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - Data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - Mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; - Data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); - - /* Wait 1ms - until band gap and ref clock ready */ - MicroSecondDelay (1000); - MemoryFence (); -} - -STATIC -VOID -ComPhyUsb3PhyConfiguration ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr -) -{ - UINT32 Mask, Data; - - /* Set PIPE soft reset */ - Mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; - Data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; - - /* Set PHY Datapath width mode for V0 */ - Mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; - Data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; - - /* Set Data bus width USB mode for V0 */ - Mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; - Data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; - - /* Set CORE_CLK output frequency for 250Mhz */ - Mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; - Data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask); - - /* Set PLL ready delay for 0x2 */ - RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, - 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, - HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); - - /* Set reference clock to come from group 1 - 25Mhz */ - RegSet (HpipeAddr + HPIPE_MISC_REG, 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, - HPIPE_MISC_REFCLK_SEL_MASK); - - /* Set reference frequcency select - 0x2 */ - Mask = HPIPE_PWR_PLL_REF_FREQ_MASK; - Data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - - /* Set PHY mode to USB - 0x5 */ - Mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; - Data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask); - - /* Set the amount of time spent in the LoZ state - set for 0x7 */ - RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL, - 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, - HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); - - /* Set max PHY generation setting - 5Gbps */ - RegSet (HpipeAddr + HPIPE_INTERFACE_REG, - 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK); - - /* Set select Data width 20Bit (SEL_BITS[2:0]) */ - RegSet (HpipeAddr + HPIPE_LOOPBACK_REG, - 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); -} - -STATIC -VOID -ComPhyUsb3SetAnalogParameters ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr -) -{ - UINT32 Data, Mask; - - /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ - Mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; - Data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; - - /* Set Override PHY DFE control pins for 0x1 */ - Mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; - Data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; - - /* Set Spread Spectrum Clock Enable fot 0x1 */ - Mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; - Data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; - RegSet (HpipeAddr + HPIPE_LANE_CFG4_REG, Data, Mask); -} - -STATIC -UINTN -ComphyUsb3PowerUp ( - UINT32 Lane, - EFI_PHYSICAL_ADDRESS HpipeBase, - EFI_PHYSICAL_ADDRESS ComPhyBase - ) -{ - EFI_STATUS Status = EFI_SUCCESS; - UINT32 Data; - EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane); - EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane); - - DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n")); - - ComPhyUsb3RFUConfiguration (ComPhyAddr); - - /* Start ComPhy Configuration */ - DEBUG((DEBUG_INFO, "stage: Comphy configuration\n")); - - ComPhyUsb3PhyConfiguration (HpipeAddr); - - /* Start analog paramters from ETP(HW) */ - DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n")); - - ComPhyUsb3SetAnalogParameters (HpipeAddr); - - DEBUG((DEBUG_INFO, "ComPhy: stage: Comphy power up\n")); - - /* Release from PIPE soft reset */ - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); - - /* Wait 15ms - for ComPhy calibration done */ - MicroSecondDelay (15000); - MemoryFence (); - - DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); - - /* Read Lane status */ - Data = MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG); - if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) == 0) { - DEBUG((DEBUG_ERROR, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n")); - Status = EFI_D_ERROR; - } - - return Status; -} - -STATIC -VOID ComPhySataMacPowerDown ( IN EFI_PHYSICAL_ADDRESS SataBase ) @@ -528,7 +366,10 @@ ComPhyCp110Init ( break; case COMPHY_TYPE_USB3_HOST0: case COMPHY_TYPE_USB3_HOST1: - Status = ComphyUsb3PowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr); + Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON, + PtrChipCfg->ComPhyBaseAddr, + Lane, + COMPHY_FW_MODE_FORMAT (COMPHY_USB3H_MODE)); break; case COMPHY_TYPE_SGMII0: case COMPHY_TYPE_SGMII1: -- 2.7.4 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
