On Thu, Jul 26, 2018 at 09:39:37AM +0200, Ard Biesheuvel wrote:
> On 26 July 2018 at 09:36, Daniel Thompson <[email protected]> wrote:
> > On Wed, Jul 25, 2018 at 12:04:58PM +0200, Ard Biesheuvel wrote:
> >> On 23 July 2018 at 15:19, Sumit Garg <[email protected]> wrote:
> >> > OP-TEE is optional on Developerbox controlled via SCP firmware. To check
> >> > if we need to delete OP-TEE DT node, we use DRAM1 region info as SCP
> >> > firmware conditionally carves out Secure memory from DRAM1 region.
> >> >
> >> > Cc: Ard Biesheuvel <[email protected]>
> >> > Cc: Leif Lindholm <[email protected]>
> >> > Contributed-under: TianoCore Contribution Agreement 1.1
> >> > Signed-off-by: Sumit Garg <[email protected]>
> >> > ---
> >> >
> >>
> >> As discussed on IRC, i am not a fan of inferring the presence of
> >> OP-TEE from the base/size values of the first DRAM region.
> >>
> >> Please refer to the existing PCIe code how to read a GPIO in PEI and
> >> set a dynamic PCD accordingly, so you can use its value in
> >> PlatformDxe.
> >
> > For Trusted Firmware I asked Sumit to look for the OP-TEE memory carve
> > out rather than looking at the switches. This was based on concerns
> > about version skew (new C-A53 firmware, old SCP firmware[1]), in particular
> > if TF-A jumps to an OP-TEE that isn't actually loaded the system will
> > fail in a not very transparent way (especially if the user hasn't found
> > the debug UART behind the back panel yet).
> >
> > What is the consequence of passing a DT with OP-TEE present if one is
> > not actually present? Do we at least get as far as bringing up the
> > framebuffer before things explode?
> >
> 
> Is there any way we can let OP-TEE supply a DT overlay?

I guess it could implement a secure monitor call to provide it. In
fact I find it a rather pleasing approach. However I think it still loops
us round to pretty much the same question as before. Does TF-A "protec
" a normal world that makes an SMC to an OP-TEE that isn't there by
failing the call in a nice way?


Daniel.
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