On Fri, Aug 24, 2018 at 12:07:18AM +0800, Ming Huang wrote:
> Add several base head files and add several build
> files for D06.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <ming.hu...@linaro.org>
> Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
> ---
> Platform/Hisilicon/D06/D06.dec | 29 ++
> Silicon/Hisilicon/Hi1620/Hi1620.dec | 23 +
> Platform/Hisilicon/D06/D06.dsc | 455
> ++++++++++++++++++++
> Platform/Hisilicon/D06/D06.fdf | 351 +++++++++++++++
> Platform/Hisilicon/D06/Include/Library/CpldD06.h | 37 ++
> Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h | 85 ++++
> Silicon/Hisilicon/Hi1620/Include/PlatformArch.h | 61 +++
> Silicon/Hisilicon/Include/Library/OemAddressMapLib.h | 6 +
> Silicon/Hisilicon/Include/Library/OemNicLib.h | 57 +++
> 9 files changed, 1104 insertions(+)
>
> diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
> new file mode 100644
> index 0000000000..9567ede0ad
> --- /dev/null
> +++ b/Platform/Hisilicon/D06/D06.fdf
> @@ -0,0 +1,351 @@
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed
> within a flash
> +# device file. This section also defines order the components and modules
> are positioned
> +# within the image. The [FV] section consists of define statements, set
> statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +BlockSize = 0x40
> +NumBlocks = 0 # This FV gets compressed so make it just big
> enough
> +FvAlignment = 16 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + APRIORI DXE {
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> + }
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> +
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> +
> +
> + INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
> + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> +
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + INF
> MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + INF
> SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
> +!endif
> +
> + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> +
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +
> + #
> + # Multiple Console IO support
> + #
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF
> MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> +
> + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + INF
> IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
> +
> + #
> + # Usb Support
> + #
> +
> +
> + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> +
> + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
> + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +
> + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
> + INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
> + INF Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
> +
> +
> +
> + INF
> Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
> +
> + INF
> Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
> +
> + #
> + #ACPI
> + #
> + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> + INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
> +
> + INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
> +
> + #
> + #Network
> + #
> +
> + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + INF NetworkPkg/TcpDxe/TcpDxe.inf
> + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +!else
> + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +!endif
> + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> +!if $(HTTP_BOOT_ENABLE) == TRUE
> + INF NetworkPkg/DnsDxe/DnsDxe.inf
> + INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
> + INF NetworkPkg/HttpDxe/HttpDxe.inf
> + INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
> +!endif
> +
> +
> + #
> + # PCI Support
> + #
> + INF Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf
> + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
> + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +
> + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
SnpDxe is included twice in this file, causing the build to fail.
Please delete this instance.
/
Leif
> + #
> + # Build Shell from latest source code instead of prebuilt binary
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> + #
> + # Bds
> + #
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> +
> + INF
> MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + APRIORI PEI {
> + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> + }
> + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
> + INF MdeModulePkg/Core/Pei/PeiMain.inf
> + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
> +
> + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
> + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
> +
> + INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
> +
> + INF ArmPkg/Drivers/CpuPei/CpuPei.inf
> + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> + INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
> +
> + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> +
> + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED
> = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> +
> +!include Silicon/Hisilicon/Hisilicon.fdf.inc
> +
> diff --git a/Platform/Hisilicon/D06/Include/Library/CpldD06.h
> b/Platform/Hisilicon/D06/Include/Library/CpldD06.h
> new file mode 100644
> index 0000000000..be3548c8d1
> --- /dev/null
> +++ b/Platform/Hisilicon/D06/Include/Library/CpldD06.h
> @@ -0,0 +1,37 @@
> +/** @file
> +
> + Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
> + Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD
> License
> + which accompanies this distribution. The full text of the license may be
> found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +
> +**/
> +
> +#ifndef __CPLDD06_H__
> +#define __CPLDD06_H__
> +
> +#define CPLD_BASE_ADDRESS 0x80000000
> +
> +#define CPLD_BIOSINDICATE_FLAG 0x09
> +#define CPLD_I2C_SWITCH_FLAG 0x17
> +#define CPU_GET_I2C_CONTROL BIT2
> +#define BMC_I2C_STATUS BIT3
> +
> +#define CPLD_LOGIC_VERSION (0x4)
> +#define CPLD_LOGIC_COMPILE_YEAR (0x1)
> +#define CPLD_LOGIC_COMPILE_MONTH (0x2)
> +#define CPLD_LOGIC_COMPILE_DAY (0x3)
> +
> +#define CPLD_RISER_PRSNT_FLAG 0x40
> +#define CPLD_RISER2_BOARD_ID 0x44
> +
> +#define CPLD_X8_X8_X8_BOARD_ID 0x92
> +#define CPLD_X16_X8_BOARD_ID 0x93
> +
> +#endif /* __CPLDD06_H__ */
> diff --git a/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h
> b/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h
> new file mode 100644
> index 0000000000..05f0f7020e
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h
> @@ -0,0 +1,85 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD
> License
> +* which accompanies this distribution. The full text of the license may be
> found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +*
> +**/
> +
> +#ifndef _SERDES_LIB_H_
> +#define _SERDES_LIB_H_
> +
> +typedef enum {
> + EmHilink0Hccs1X8 = 0,
> + EmHilink0Pcie1X8 = 2,
> + EmHilink0Pcie1X4Pcie2X4 = 3,
> + EmHilink0Sas2X8 = 4,
> + EmHilink0Hccs1X8Width16,
> + EmHilink0Hccs1X8Width32,
> + EmHilink0Hccs1X8Speed5G,
> +} HILINK0_MODE_TYPE;
> +
> +typedef enum {
> + EmHilink1Sas2X1 = 0,
> + EmHilink1Hccs0X8 = 1,
> + EmHilink1Pcie0X8 = 2,
> + EmHilink1Hccs0X8Width16,
> + EmHilink1Hccs0X8Width32,
> + EmHilink1Hccs0X8Speed5G,
> +} HILINK1_MODE_TYPE;
> +
> +typedef enum {
> + EmHilink2Pcie2X8 = 0,
> + EmHilink2Hccs2X8 = 1,
> + EmHilink2Sas0X8 = 2,
> + EmHilink2Hccs2X8Width16,
> + EmHilink2Hccs2X8Width32,
> + EmHilink2Hccs2X8Speed5G,
> +} HILINK2_MODE_TYPE;
> +
> +typedef enum {
> + EmHilink5Pcie3X4 = 0,
> + EmHilink5Pcie2X2Pcie3X2 = 1,
> + EmHilink5Sas1X4 = 2,
> +} HILINK5_MODE_TYPE;
> +
> +
> +typedef struct {
> + HILINK0_MODE_TYPE Hilink0Mode;
> + HILINK1_MODE_TYPE Hilink1Mode;
> + HILINK2_MODE_TYPE Hilink2Mode;
> + UINT32 Hilink3Mode;
> + UINT32 Hilink4Mode;
> + HILINK5_MODE_TYPE Hilink5Mode;
> + UINT32 Hilink6Mode;
> + UINT32 UseSsc;
> +} SERDES_PARAM;
> +
> +#define SERDES_INVALID_MACRO_ID 0xFFFFFFFF
> +#define SERDES_INVALID_LANE_NUM 0xFFFFFFFF
> +#define SERDES_INVALID_RATE_MODE 0xFFFFFFFF
> +
> +typedef struct {
> + UINT32 MacroId;
> + UINT32 DsNum;
> + UINT32 DsCfg;
> +} SERDES_POLARITY_INVERT;
> +
> +EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB,
> UINT32 SocketId);
> +extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
> +extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
> +UINT32 GetEthType (UINT8 EthChannel);
> +VOID SerdesEnableCtleDfe (UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32
> LaneMode);
> +
> +EFI_STATUS EfiSerdesInitWrap (UINT32 RateMode);
> +INT32 SerdesReset (UINT32 SiclId, UINT32 Macro);
> +VOID SerdesLoadFirmware (UINT32 SiclId, UINT32 Macro);
> +INT32 h30_serdes_run_firmware (UINT32 nimbus_id, UINT32 macro, UINT8 DsMask,
> UINT8 ctle_mode);
> +#endif
> diff --git a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
> b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
> new file mode 100644
> index 0000000000..9539cfdada
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
> @@ -0,0 +1,61 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD
> License
> +* which accompanies this distribution. The full text of the license may be
> found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +*
> +**/
> +
> +
> +
> +#ifndef _PLATFORM_ARCH_H_
> +#define _PLATFORM_ARCH_H_
> +
> +#define MAX_SOCKET 2
> +#define MAX_DIE 4
> +#define MAX_DDRC 4
> +#define MAX_NODE (MAX_SOCKET * MAX_DIE)
> +#define MAX_CHANNEL 8
> +#define MAX_DIMM 2
> +#define MAX_RANK_CH 8
> +#define MAX_RANK_DIMM 4
> +#define MAX_DIMM_SIZE 256 // In GB
> +// Max NUMA node number for each node type
> +#define MAX_NUM_PER_TYPE 8
> +
> +#define RASC_BASE (0x1800)
> +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x58) /* configuration
> register for Rank statistical information */
> +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xD4) /* configuration
> register for Sparing level */
> +
> +//
> +// ACPI table information used to initialize tables.
> +//
> +#define EFI_ACPI_ARM_OEM_ID 'H','I','S','I',' ',' ' // OEMID 6
> bytes long
> +#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64 ('H','I','P','0','8','
> ',' ',' ') // OEM table id 8 bytes long
> +#define EFI_ACPI_ARM_OEM_REVISION 0x00000000
> +#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32 ('H','I','S','I')
> +#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
> +
> +// A macro to initialise the common header part of EFI ACPI tables as
> defined by
> +// EFI_ACPI_DESCRIPTION_HEADER structure.
> +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
> + Signature, /* UINT32 Signature */ \
> + sizeof (Type), /* UINT32 Length */ \
> + Revision, /* UINT8 Revision */ \
> + 0, /* UINT8 Checksum */ \
> + { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
> + EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
> + EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
> + EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
> + EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
> + }
> +
> +#endif
> +
> diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
> b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
> index 21498b7056..332a79343f 100644
> --- a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
> +++ b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
> @@ -27,7 +27,13 @@ typedef struct _DDRC_BASE_ID{
> UINTN OemGetPoeSubBase (UINT32 NodeId);
> UINTN OemGetPeriSubBase (UINT32 NodeId);
> UINTN OemGetAlgSubBase (UINT32 NodeId);
> +UINTN OemGetCfgbusBase (UINT32 NodeId);
> +UINTN OemGetGicSubBase (UINT32 NodeId);
> +UINTN OemGetHACSubBase (UINT32 NodeId);
> +UINTN OemGetIOMGMTSubBase (UINT32 NodeId);
> +UINTN OemGetNetworkSubBase (UINT32 NodeId);
> UINTN OemGetM3SubBase (UINT32 NodeId);
> +UINTN OemGetPCIeSubBase (UINT32 NodeId);
>
> VOID OemAddressMapInit(VOID);
>
> diff --git a/Silicon/Hisilicon/Include/Library/OemNicLib.h
> b/Silicon/Hisilicon/Include/Library/OemNicLib.h
> new file mode 100644
> index 0000000000..66fe9a2e9b
> --- /dev/null
> +++ b/Silicon/Hisilicon/Include/Library/OemNicLib.h
> @@ -0,0 +1,57 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD
> License
> +* which accompanies this distribution. The full text of the license may be
> found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +*
> +**/
> +
> +
> +#ifndef _OEM_NIC_LIB_H_
> +#define _OEM_NIC_LIB_H_
> +
> +#define ETH_MAX_PORT 8
> +#define ETH_DEBUG_PORT0 6
> +#define ETH_DEBUG_PORT1 7
> +
> +#define ETH_SPEED_10M 6
> +#define ETH_SPEED_100M 7
> +#define ETH_SPEED_1000M 8
> +#define ETH_SPEED_10KM 9
> +#define ETH_HALF_DUPLEX 0
> +#define ETH_FULL_DUPLEX 1
> +
> +#define ETH_GDD_ID 0x001378e0
> +#define ETH_PHY_BCM5241_ID 0x0143bc30
> +#define ETH_PHY_MVL88E1145_ID 0x01410cd0
> +#define ETH_PHY_MVL88E1119_ID 0x01410e80
> +#define ETH_PHY_MVL88E1512_ID 0x01410dd0
> +#define ETH_PHY_MVL88E1543_ID 0x01410ea0
> +#define ETH_PHY_NLP3142_ID 0x00000412
> +
> +#define ETH_INVALID 0xffffffff
> +
> +typedef struct {
> + UINT32 Valid;
> + UINT32 Speed;
> + UINT32 Duplex;
> + UINT32 PhyId;
> + UINT32 PhyAddr;
> +} ETH_PRODUCT_DESC;
> +
> +BOOLEAN OemIsInitEth (UINT32 Port);
> +UINT32 OemEthFindFirstSP ();
> +ETH_PRODUCT_DESC *OemEthInit (UINT32 port);
> +UINT32 GetCpu1FiberType (UINT8 *Fiber1Type, UINT8 *Fiber2Type);
> +UINT32 GetCpu2FiberType (UINT8 *Fiber1Type, UINT8 *Fiber2Type, UINT8
> *Fiber100Ge);
> +EFI_STATUS EFIAPI OemGetMac (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port);
> +EFI_STATUS EFIAPI OemSetMac (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port);
> +
> +#endif
> --
> 2.18.0
>
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