On Tue, Oct 30, 2018 at 09:39:24AM -0300, Ard Biesheuvel wrote:
> (add back the list)

Oi! Go back on holiday!

> On 30 October 2018 at 09:07, Cohen, Eugene <[email protected]> wrote:
> > Has this patch been tested on a system that does not have coherent DMA?
> >
> > It's not clear that this change would actually be faster on a system of that
> > type since using common buffers imply access to uncached memory.  Depending
> > on the access patterns the uncached memory access could be more time
> > consuming than cache maintenance operations.
> 
> I haven't had time to look at these patches yet.
> 
> I agree with Eugene's concern: the directional DMA routines are much
> more performant on implementations with non-coherent DMA, and so
> common buffers should be avoided unless we are dealing with data
> structures that are truly shared between the CPU and the device.
> 
> Since this is obviously not the case here, could we please have some
> numbers about the performance improvement we are talking about here?
> Would it be possible to improve the IOMMU handling code instead?

On an unrelated note to the concerns above:
Why has a fundamental change to the behaviour of one of the industry
standard drivers been pushed at the very end of the stable cycle?

Regards,

Leif
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