BaseIoLibIntrinsicArmVirt was created to prevent LTO from merging accesses to MMIO regions, resulting in instructions with multiple output registers that KVM on ARM cannot emulate (since the exception syndrome information that KVM relies on can only describe a single output register)
However, using double word loads on ARM amounts to the same thing, and so code that relies on doing 64-bit MMIO to regions that are emulated under KVM (such as the GICv3 TYPER register) will still suffer from the original issue. So replace ldrd and strd with equivalent two instruction sequences. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <[email protected]> --- MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S index 3ad22bd5706d..0d802d6928d6 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.S @@ -125,7 +125,8 @@ ASM_PFX(MmioWrite32Internal): // @return The value read. // ASM_PFX(MmioRead64Internal): - ldrd r0, r1, [r0] + ldr r1, [r0, #4] + ldr r0, [r0] dmb bx lr @@ -141,5 +142,6 @@ ASM_PFX(MmioRead64Internal): // ASM_PFX(MmioWrite64Internal): dmb st - strd r2, r3, [r0] + str r2, [r0] + str r3, [r0, #4] bx lr -- 2.19.1 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
