(+ Marc)
On 29 October 2018 at 05:57, Ming Huang <ming.hu...@linaro.org> wrote:
> As GicV3 Spec, Interrupt Routing Modes should be 0 for
> routing the SPIs to the primary CPU.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <ming.hu...@linaro.org>
> ---
> ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
> b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
> index 01154848f443..1558db31713a 100644
> --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
> +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
> @@ -469,7 +469,7 @@ GicV3DxeInitialize (
> for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
> MmioWrite32 (
> mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8),
> - CpuTarget | ARM_GICD_IROUTER_IRM
> + CpuTarget
> );
> }
> }
> --
> 2.18.0
>
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