On 11/14/2018 9:05 AM, Leif Lindholm wrote:
> +Prasanth
>
> On Mon, Oct 29, 2018 at 11:51:11AM +0800, Ming Huang wrote:
>> PE test case 15 flow:
>> Primary core(cacheable shareable) and slave cores(non-cacheable)
>> access the same memory area for communication.
>> For each slave core{
>> 1 Turn on slave core;
>> 2 run the payload function;
>> 3 Write result in memory to notify primary core and follow
>> clean and invalid instruction;
>
> clean and invalidate
>
>> 4 Slave core turn off itself;
>> }
>> The result in DDR may rewrite by cache data. The essence of
>> this problem is that primary core and slave core access the
>> same area with different cache attribute.
>> Configure L3T register to fix this issue;
>
> Does this change have any performance implications?
Feedback by chip engineer, performance may be reduced a bit.
>
> Prasanth: would PE test 15 not be _expected_ to fail if primary and
> secondary cores access the buffers with different cachability
> attributes?
>
>> Build commit informations:
>> edk2:53caffc33b6
>> edk2-platforms:d4d7e39886a
>> HwPgk:6e91ea20fda
>
> HwPkg.
>
> /
> Leif
>
>> TrustedFirmware:5888a78d43c
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ming Huang <[email protected]>
>> ---
>> Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi | Bin 230784 ->
>> 230816 bytes
>> 1 file changed, 0 insertions(+), 0 deletions(-)
>>
>> diff --git a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi
>> b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi
>> index 8b6d740..b5aa0aa 100644
>> Binary files a/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi and
>> b/Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.efi differ
>> --
>> 2.18.0
>>
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