> -----Original Message----- > From: edk2-devel [mailto:[email protected]] On Behalf Of > Ashish Singhal > Sent: Friday, November 30, 2018 3:15 AM > To: [email protected] > Cc: Ashish Singhal > Subject: [edk2] [PATCH v6 1/2] MdeModulePkg/SdMmcPciHcDxe: Declare V4 > 64 bit address capability > > Add capability declaration for V4.x 64 bit system address support. > This would be used for host controllers working in version 4. Enable > 64 bit DMA support in PCI layer if V3 or V4 64 bit support is > enabled in host capability register. > > The usage of this new field does not need a guard for version check as > spec for previous SDMMC versions defines this field as reserved with > default value of 0. > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1359 > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ashish Singhal <[email protected]> > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 9 ++++++++- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 3 ++- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 10 +++++----- > 3 files changed, 15 insertions(+), 7 deletions(-) > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > index a87f8de..2bfd758 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > @@ -649,7 +649,14 @@ SdMmcPciHcDriverBindingStart ( > Private->BaseClkFreq[Slot] > )); > > - Support64BitDma &= Private->Capability[Slot].SysBus64; > + // > + // If any of the slots does not support 64b system bus > + // do not enable 64b DMA in the PCI layer. > + // > + if (Private->Capability[Slot].SysBus64V3 == 0 &&^M > + Private->Capability[Slot].SysBus64V4 == 0) {^M > + Support64BitDma &= FALSE;^M
The above lines seem not well-formatted at EOL. With the that addressed: Reviewed-by: Hao Wu <[email protected]> Best Regards, Hao Wu > + } > > Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private- > >MaxCurrent[Slot]); > if (EFI_ERROR (Status)) { > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > index ddf6dcf..598b6a3 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > @@ -45,7 +45,8 @@ DumpCapabilityReg ( > DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? > "TRUE" : "FALSE")); > DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? > "TRUE" : "FALSE")); > DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? > "TRUE" : "FALSE")); > - DEBUG ((DEBUG_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 ? > "TRUE" : "FALSE")); > + DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? > "TRUE" : "FALSE")); > + DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? > "TRUE" : "FALSE")); > DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? > "TRUE" : "FALSE")); > DEBUG ((DEBUG_INFO, " SlotType ")); > if (Capability->SlotType == 0x00) { > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > index dd45cbd..ad9ce64 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > @@ -129,24 +129,24 @@ typedef struct { > UINT32 Voltage33:1; // bit 24 > UINT32 Voltage30:1; // bit 25 > UINT32 Voltage18:1; // bit 26 > - UINT32 Reserved3:1; // bit 27 > - UINT32 SysBus64:1; // bit 28 > + UINT32 SysBus64V4:1; // bit 27 > + UINT32 SysBus64V3:1; // bit 28 > UINT32 AsyncInt:1; // bit 29 > UINT32 SlotType:2; // bit 30:31 > UINT32 Sdr50:1; // bit 32 > UINT32 Sdr104:1; // bit 33 > UINT32 Ddr50:1; // bit 34 > - UINT32 Reserved4:1; // bit 35 > + UINT32 Reserved3:1; // bit 35 > UINT32 DriverTypeA:1; // bit 36 > UINT32 DriverTypeC:1; // bit 37 > UINT32 DriverTypeD:1; // bit 38 > UINT32 DriverType4:1; // bit 39 > UINT32 TimerCount:4; // bit 40:43 > - UINT32 Reserved5:1; // bit 44 > + UINT32 Reserved4:1; // bit 44 > UINT32 TuningSDR50:1; // bit 45 > UINT32 RetuningMod:2; // bit 46:47 > UINT32 ClkMultiplier:8; // bit 48:55 > - UINT32 Reserved6:7; // bit 56:62 > + UINT32 Reserved5:7; // bit 56:62 > UINT32 Hs400:1; // bit 63 > } SD_MMC_HC_SLOT_CAP; > > -- > 2.7.4 > > _______________________________________________ > edk2-devel mailing list > [email protected] > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
