Use the correct value for ARM_GICD_IROUTER as per the GIC spec, and fix the code that relies on the value being skewed by 32 x 8 bytes.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <[email protected]> --- ArmPkg/Include/Library/ArmGicLib.h | 2 +- ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h index 5775905ca91b..b52b77628ae1 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -43,7 +43,7 @@ #define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register // GICv3 specific registers -#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers +#define ARM_GICD_IROUTER 0x6000 // Interrupt Routing Registers // GICD_CTLR bits #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE) diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 1558db31713a..7d891873ba82 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -466,7 +466,7 @@ GicV3DxeInitialize ( } // Route the SPIs to the primary CPU. SPIs start at the INTID 32 - for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { + for (Index = 32; Index < mGicNumInterrupts; Index++) { MmioWrite32 ( mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget -- 2.19.2 _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
