Recent changes in the ARM-TF configure its runtime serices region
as protected, hence the hitherto PEI stack base address (0x41F0000)
violated it. Additional region needs to also be reserved to cover
OP-TEE
In order to fix this, add more regions which are non-accessible
by the OS to cover:
* the ARM-TF (0x4000000 - 0x4200000)
* OP-TEE (0x4400000 - 0x5400000)
* additional reserved region (0x4200000 - 0x4400000)
Describe regions with the new PCDs and set the PEI stack base address
in the latter (0x43F0000).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
---
Silicon/Marvell/Marvell.dec
| 8 ++++++--
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
| 16 ++++++++++++----
Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
| 8 ++++++--
Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
| 18 +++++++++++++++---
4 files changed, 39 insertions(+), 11 deletions(-)
diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec
index c34d783..c927078 100644
--- a/Silicon/Marvell/Marvell.dec
+++ b/Silicon/Marvell/Marvell.dec
@@ -211,8 +211,12 @@
# normal world. These PCDs describe such a region, which will be converted
# to 'reserved' memory before DXE is entered.
#
- gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x0|UINT64|0x50000000
- gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0|UINT32|0x50000001
+ gMarvellTokenSpaceGuid.PcdArmTFRegionBase|0x0|UINT64|0x50000000
+ gMarvellTokenSpaceGuid.PcdArmTFRegionSize|0x0|UINT32|0x50000001
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x0|UINT64|0x50000002
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x0|UINT32|0x50000003
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionBase|0x0|UINT64|0x50000004
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionSize|0x0|UINT32|0x50000005
[Protocols]
gMarvellBoardDescProtocolGuid = { 0xebed8738, 0xd4a6, 0x4001, {
0xa9, 0xc9, 0x52, 0xb0, 0xcb, 0x7d, 0xdb, 0xf9 }}
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
index eafcd6e..1e2d248 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -376,12 +376,20 @@
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|36
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x41F0000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x43F0000
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
- # Secure region reservation
- gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000
- gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0200000
+ # ARM-TF region reservation
+ gMarvellTokenSpaceGuid.PcdArmTFRegionBase|0x4000000
+ gMarvellTokenSpaceGuid.PcdArmTFRegionSize|0x200000
+
+ # Additional region reservation (e.g. for PEI stack base)
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase|0x4200000
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize|0x200000
+
+ # OP-TEE region reservation
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionBase|0x4400000
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionSize|0x1000000
# TRNG
gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000
diff --git
a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
index 096495d..360de90 100644
---
a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
+++
b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf
@@ -42,5 +42,9 @@
gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
[FixedPcd]
- gMarvellTokenSpaceGuid.PcdSecureRegionBase
- gMarvellTokenSpaceGuid.PcdSecureRegionSize
+ gMarvellTokenSpaceGuid.PcdArmTFRegionBase
+ gMarvellTokenSpaceGuid.PcdArmTFRegionSize
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionBase
+ gMarvellTokenSpaceGuid.PcdAuxiliaryReservedRegionSize
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionBase
+ gMarvellTokenSpaceGuid.PcdOpTeeRegionSize
diff --git
a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
index 3e7902f..571f77e 100644
---
a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
+++
b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.c
@@ -167,10 +167,22 @@ MemoryPeim (
// Get Virtual Memory Map from the Platform Library
ArmPlatformGetVirtualMemoryMap (&MemoryTable);
- // Reserve memory region for secure firmware
+ // Reserve memory region for ARM-TF
ReserveMemoryRegion (
- (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdSecureRegionBase),
- FixedPcdGet32 (PcdSecureRegionSize)
+ (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdArmTFRegionBase),
+ FixedPcdGet32 (PcdArmTFRegionSize)
+ );
+
+ // Reserve additional memory region (e.g. for PEI stack)
+ ReserveMemoryRegion (
+ (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdAuxiliaryReservedRegionBase),
+ FixedPcdGet32 (PcdAuxiliaryReservedRegionSize)
+ );
+
+ // Reserve memory region for OP-TEE
+ ReserveMemoryRegion (
+ (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdOpTeeRegionBase),
+ FixedPcdGet32 (PcdOpTeeRegionSize)
);
// Build Memory Allocation Hob
--
2.7.4
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