Follow chip team suggestion to change HCCS(Huawei Cache-Coherent
System) speed from 30G to 26G, this modification can avoid some
unstable stress issue.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.hu...@linaro.org>
---
Silicon/Hisilicon/Include/Library/OemMiscLib.h | 10 ++++++++++
Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 8 ++++++++
2 files changed, 18 insertions(+)
diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h
b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
index dfac87d635d9..3c0cd0319122 100644
--- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
@@ -22,6 +22,11 @@
#include <PlatformArch.h>
#include <Library/I2CLib.h>
+#define HCCS_PLL_VALUE_3000 0x52240781
+#define HCCS_PLL_VALUE_2600 0x52240681
+#define HCCS_PLL_VALUE_2800 0x52240701
+
+
#define PCIEDEVICE_REPORT_MAX 8
#define MAX_PROCESSOR_SOCKETS MAX_SOCKET
#define MAX_MEMORY_CHANNELS MAX_CHANNEL
@@ -55,4 +60,9 @@ extern EFI_STRING_ID
gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM];
EFI_HII_HANDLE EFIAPI OemGetPackages ();
UINTN OemGetCpuFreq (UINT8 Socket);
+UINTN
+OemGetHccsFreq (
+ VOID
+ );
+
#endif
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
index 8f2ac308c7b9..83e53cfeb5dd 100644
--- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
@@ -223,3 +223,11 @@ UINTN OemGetCpuFreq (UINT8 Socket)
}
}
+UINTN
+OemGetHccsFreq (
+ VOID
+ )
+{
+ return HCCS_PLL_VALUE_2600;
+}
+
--
2.9.5
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