Reviewed-by: Benjamin You <[email protected]>
> -----Original Message----- > From: edk2-devel [mailto:[email protected]] On Behalf Of > Antoine Coeur > Sent: Thursday, February 7, 2019 12:49 AM > To: [email protected] > Subject: [edk2] [PATCH] CorebootPayloadPkg: Fix various typos > > Fix various typos in CorebootPayloadPkg. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Coeur <[email protected]> > --- > CorebootPayloadPkg/FbGop/FbGop.c | 8 +- > CorebootPayloadPkg/FbGop/FbGop.h | 8 +- > .../Library/PciHostBridgeLib/PciHostBridge.h | 2 +- > .../PciHostBridgeLib/PciHostBridgeLib.c | 2 +- > .../PciHostBridgeLib/PciHostBridgeSupport.c | 6 +- > .../PlatformBootManager.c | 2 +- > .../Library/PlatformHookLib/PlatformHookLib.c | 106 +++++++++--------- > 7 files changed, 67 insertions(+), 67 deletions(-) > > diff --git a/CorebootPayloadPkg/FbGop/FbGop.c > b/CorebootPayloadPkg/FbGop/FbGop.c > index ecafc95ae3..9a66943cbf 100644 > --- a/CorebootPayloadPkg/FbGop/FbGop.c > +++ b/CorebootPayloadPkg/FbGop/FbGop.c > @@ -262,7 +262,7 @@ FbGopDriverBindingStart ( > if (IsDevicePathEnd (RemainingDevicePath)) { > // > // If RemainingDevicePath is the End of Device Path Node, > - // don't create any child device and return EFI_SUCESS > + // don't create any child device and return EFI_SUCCESS > Status = EFI_SUCCESS; > goto Done; > } > @@ -688,7 +688,7 @@ FbGopChildHandleUninstall ( > > > /** > - Release resource for biso video instance. > + Release resource for bios video instance. > > @param FbGopPrivate Video child device private data structure > > @@ -703,7 +703,7 @@ FbGopDeviceReleaseResource ( > } > > // > - // Release all the resourses occupied by the FB_VIDEO_DEV > + // Release all the resources occupied by the FB_VIDEO_DEV > // > > // > @@ -1222,7 +1222,7 @@ FbGopVbeBltWorker ( > } > // > // We need to fill the Virtual Screen buffer with the blt data. > - // The virtual screen is upside down, as the first row is the bootom row of > + // The virtual screen is upside down, as the first row is the bottom row of > // the image. > // > if (BltOperation == EfiBltVideoToBltBuffer) { > diff --git a/CorebootPayloadPkg/FbGop/FbGop.h > b/CorebootPayloadPkg/FbGop/FbGop.h > index 4445f5c730..112d5c5cb5 100644 > --- a/CorebootPayloadPkg/FbGop/FbGop.h > +++ b/CorebootPayloadPkg/FbGop/FbGop.h > @@ -205,7 +205,7 @@ FbGopCheckForVbe ( > > > /** > - Release resource for biso video instance. > + Release resource for bios video instance. > > @param FbGopPrivate Video child device private data structure > > @@ -311,9 +311,9 @@ FbGopGraphicsOutputVbeBlt ( > > > /** > - Grahpics Output protocol instance to block transfer for VGA device. > + Graphics Output protocol instance to block transfer for VGA device. > > - @param This Pointer to Grahpics Output protocol instance > + @param This Pointer to Graphics Output protocol instance > @param BltBuffer The data to transfer to screen > @param BltOperation The operation to perform > @param SourceX The X coordinate of the source for > BltOperation > @@ -394,7 +394,7 @@ FbGopChildHandleUninstall ( > ); > > /** > - Release resource for biso video instance. > + Release resource for bios video instance. > > @param FbGopPrivate Video child device private data structure > > diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h > b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h > index 4852ed0d8d..c777cdbac1 100644 > --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h > +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h > @@ -42,7 +42,7 @@ ScanForRootBridges ( > assigned to any subordinate bus found behind > any > PCI bridge hanging off this root bus. > > - The caller is repsonsible for ensuring that > + The caller is responsible for ensuring that > RootBusNumber <= MaxSubBusNumber. If > RootBusNumber equals MaxSubBusNumber, then the > root bus has no room for subordinate buses. > diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c > b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c > index b0a6361557..f7e1369a08 100644 > --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c > +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c > @@ -70,7 +70,7 @@ CB_PCI_ROOT_BRIDGE_DEVICE_PATH > mRootBridgeDevicePathTemplate = { > assigned to any subordinate bus found behind > any > PCI bridge hanging off this root bus. > > - The caller is repsonsible for ensuring that > + The caller is responsible for ensuring that > RootBusNumber <= MaxSubBusNumber. If > RootBusNumber equals MaxSubBusNumber, then the > root bus has no room for subordinate buses. > diff --git > a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > index 18dcbafdf0..d06db1e12e 100644 > --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > @@ -146,7 +146,7 @@ PcatPciRootBridgeBarExisted ( > } > > /** > - Parse PCI bar and collect the assigned PCI resouce information. > + Parse PCI bar and collect the assigned PCI resource information. > > @param[in] Command Supported attributes. > > @@ -397,7 +397,7 @@ ScanForRootBridges ( > // > if (Pci.Bridge.SubordinateBus > SubBus) { > // > - // If the suborinate bus number of the PCI-PCI bridge is greater > + // If the subordinate bus number of the PCI-PCI bridge is greater > // than the PCI root bridge's current subordinate bus number, > // then update the PCI root bridge's subordinate bus number > // > @@ -536,7 +536,7 @@ ScanForRootBridges ( > > // > // See if the PCI Device is a PCI - ISA or PCI - EISA > - // or ISA_POSITIVIE_DECODE Bridge device > + // or ISA_POSITIVE_DECODE Bridge device > // > if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) { > if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA || > diff --git > a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManage > r.c > b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManage > r.c > index 368e89d586..0b180dad32 100644 > --- > a/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManage > r.c > +++ > b/CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManage > r.c > @@ -208,7 +208,7 @@ PlatformBootManagerBeforeConsole ( > Signal console ready platform customized event; > Run diagnostics like memory testing; > Connect certain devices; > - Dispatch aditional option roms. > + Dispatch additional option roms. > **/ > VOID > EFIAPI > diff --git a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c > b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c > index b1cfb8e2c0..83bf0eba08 100644 > --- a/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c > +++ b/CorebootPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c > @@ -14,27 +14,27 @@ > > #include <Base.h> > #include <Uefi/UefiBaseType.h> > -#include <Library/PciLib.h> > +#include <Library/PciLib.h> > #include <Library/PlatformHookLib.h> > #include <Library/CbParseLib.h> > #include <Library/PcdLib.h> > > -typedef struct { > - UINT16 VendorId; ///< Vendor ID to match the PCI device. The > value > 0xFFFF terminates the list of entries. > - UINT16 DeviceId; ///< Device ID to match the PCI device > - UINT32 ClockRate; ///< UART clock rate. Set to 0 for default > clock rate > of 1843200 Hz > - UINT64 Offset; ///< The byte offset into to the BAR > - UINT8 BarIndex; ///< Which BAR to get the UART base address > - UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 > for default > register stride of 1 byte. > - UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 > for > a default FIFO depth of 16 bytes. > - UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 > for a default FIFO depth of 16 bytes. > - UINT8 Reserved[2]; > -} PCI_SERIAL_PARAMETER; > - > +typedef struct { > + UINT16 VendorId; ///< Vendor ID to match the PCI device. The > value > 0xFFFF terminates the list of entries. > + UINT16 DeviceId; ///< Device ID to match the PCI device > + UINT32 ClockRate; ///< UART clock rate. Set to 0 for default > clock rate > of 1843200 Hz > + UINT64 Offset; ///< The byte offset into to the BAR > + UINT8 BarIndex; ///< Which BAR to get the UART base address > + UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 > for > default register stride of 1 byte. > + UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 > for a default FIFO depth of 16 bytes. > + UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 > for a default FIFO depth of 16 bytes. > + UINT8 Reserved[2]; > +} PCI_SERIAL_PARAMETER; > + > /** > Performs platform specific initialization required for the CPU to access > the hardware associated with a SerialPortLib instance. This function does > - not intiailzie the serial port hardware itself. Instead, it initializes > + not initialize the serial port hardware itself. Instead, it initializes > hardware devices that are required for the CPU to access the serial port > hardware. This function may be called more than once. > > @@ -51,16 +51,16 @@ PlatformHookSerialPortInitialize ( > RETURN_STATUS Status; > UINT32 SerialRegBase; > UINT32 SerialRegAccessType; > - UINT32 BaudRate; > - UINT32 RegWidth; > - UINT32 InputHertz; > - UINT32 PayloadParam; > - UINT32 DeviceVendor; > - PCI_SERIAL_PARAMETER *SerialParam; > - > - Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType, > - &RegWidth, &BaudRate, &InputHertz, > - &PayloadParam); > + UINT32 BaudRate; > + UINT32 RegWidth; > + UINT32 InputHertz; > + UINT32 PayloadParam; > + UINT32 DeviceVendor; > + PCI_SERIAL_PARAMETER *SerialParam; > + > + Status = CbParseSerialInfo (&SerialRegBase, &SerialRegAccessType, > + &RegWidth, &BaudRate, &InputHertz, > + &PayloadParam); > if (RETURN_ERROR (Status)) { > return Status; > } > @@ -78,34 +78,34 @@ PlatformHookSerialPortInitialize ( > return Status; > } > > - Status = PcdSet32S (PcdSerialRegisterStride, RegWidth); > - if (RETURN_ERROR (Status)) { > - return Status; > - } > - > - Status = PcdSet32S (PcdSerialBaudRate, BaudRate); > - if (RETURN_ERROR (Status)) { > - return Status; > - } > - > - Status = PcdSet64S (PcdUartDefaultBaudRate, BaudRate); > - if (RETURN_ERROR (Status)) { > - return Status; > - } > - > - Status = PcdSet32S (PcdSerialClockRate, InputHertz); > - if (RETURN_ERROR (Status)) { > - return Status; > - } > - > - if (PayloadParam >= 0x80000000) { > - DeviceVendor = PciRead32 (PayloadParam & 0x0ffff000); > - SerialParam = PcdGetPtr(PcdPciSerialParameters); > - SerialParam->VendorId = (UINT16)DeviceVendor; > - SerialParam->DeviceId = DeviceVendor >> 16; > - SerialParam->ClockRate = InputHertz; > - SerialParam->RegisterStride = (UINT8)RegWidth; > - } > - > + Status = PcdSet32S (PcdSerialRegisterStride, RegWidth); > + if (RETURN_ERROR (Status)) { > + return Status; > + } > + > + Status = PcdSet32S (PcdSerialBaudRate, BaudRate); > + if (RETURN_ERROR (Status)) { > + return Status; > + } > + > + Status = PcdSet64S (PcdUartDefaultBaudRate, BaudRate); > + if (RETURN_ERROR (Status)) { > + return Status; > + } > + > + Status = PcdSet32S (PcdSerialClockRate, InputHertz); > + if (RETURN_ERROR (Status)) { > + return Status; > + } > + > + if (PayloadParam >= 0x80000000) { > + DeviceVendor = PciRead32 (PayloadParam & 0x0ffff000); > + SerialParam = PcdGetPtr(PcdPciSerialParameters); > + SerialParam->VendorId = (UINT16)DeviceVendor; > + SerialParam->DeviceId = DeviceVendor >> 16; > + SerialParam->ClockRate = InputHertz; > + SerialParam->RegisterStride = (UINT8)RegWidth; > + } > + > return RETURN_SUCCESS; > } > -- > 2.17.2 (Apple Git-113) > > _______________________________________________ > edk2-devel mailing list > [email protected] > https://lists.01.org/mailman/listinfo/edk2-devel _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
