Clear the CD (Cache Disable) flag in the CR0 register. When the VM
implements the CD flag, this can substantially decrease the time it
takes to decompress the firmware volumes.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Tested-by: Peter Fang <peter.f...@intel.com>
Cc: Peter Fang <peter.f...@intel.com>
Cc: Maurice Ma <maurice...@intel.com>
Cc: Laszlo Ersek <ler...@redhat.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Anthony Perard <anthony.per...@citrix.com>
Cc: Julien Grall <julien.gr...@linaro.org>
---
OvmfPkg/Sec/Ia32/SecEntry.nasm | 8 +++++++-
OvmfPkg/Sec/X64/SecEntry.nasm | 8 +++++++-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/OvmfPkg/Sec/Ia32/SecEntry.nasm b/OvmfPkg/Sec/Ia32/SecEntry.nasm
index 03501969eb..fc7f47385a 100644
--- a/OvmfPkg/Sec/Ia32/SecEntry.nasm
+++ b/OvmfPkg/Sec/Ia32/SecEntry.nasm
@@ -40,6 +40,13 @@ extern ASM_PFX(SecCoreStartupWithStack)
global ASM_PFX(_ModuleEntryPoint)
ASM_PFX(_ModuleEntryPoint):
+ ;
+ ; Clear the CD (Cache Disable) flag in the CR0 register.
+ ;
+ mov eax, cr0
+ and eax, ~(1 << 30)
+ mov cr0, eax
+
;
; Fill the temporary RAM with the initial stack value.
; The loop below will seed the heap as well, but that's harmless.
@@ -71,4 +78,3 @@ ASM_PFX(_ModuleEntryPoint):
push eax
push ebp
call ASM_PFX(SecCoreStartupWithStack)
-
diff --git a/OvmfPkg/Sec/X64/SecEntry.nasm b/OvmfPkg/Sec/X64/SecEntry.nasm
index d76adcffd8..7471b3a3e3 100644
--- a/OvmfPkg/Sec/X64/SecEntry.nasm
+++ b/OvmfPkg/Sec/X64/SecEntry.nasm
@@ -41,6 +41,13 @@ extern ASM_PFX(SecCoreStartupWithStack)
global ASM_PFX(_ModuleEntryPoint)
ASM_PFX(_ModuleEntryPoint):
+ ;
+ ; Clear the CD (Cache Disable) flag in the CR0 register.
+ ;
+ mov rax, cr0
+ and eax, ~(1 << 30)
+ mov cr0, rax
+
;
; Fill the temporary RAM with the initial stack value.
; The loop below will seed the heap as well, but that's harmless.
@@ -72,4 +79,3 @@ ASM_PFX(_ModuleEntryPoint):
mov rdx, rsp
sub rsp, 0x20
call ASM_PFX(SecCoreStartupWithStack)
-
--
2.20.1
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