BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621
According to Intel SDM as below, the BIT0 should be treated as lock bit, and BIT1 should be treated as disable(0)/enable(1) bit. "11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b" Cc: Laszlo Ersek <ler...@redhat.com> Cc: Eric Dong <eric.d...@intel.com> Cc: Ruiyu Ni <ruiyu...@intel.com> Cc: Chandana Kumar <chandana.c.ku...@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.z...@intel.com> --- UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c index 56b1b551d977..3f7c933e51f4 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c @@ -1,7 +1,7 @@ /** @file AESNI feature. - Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -123,7 +123,7 @@ AesniInitialize ( MSR_SANDY_BRIDGE_FEATURE_CONFIG, MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER, Bits.AESConfiguration, - BIT1 | ((State) ? 0 : BIT0) + BIT0 | ((State) ? 0 : BIT1) ); } } -- 2.21.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel