Per 2c4b18e ("MdeModulePkg: Add the alignment check for FTW spare area
address and length, and add the check for PcdFlashNvStorageVariableSize
<= PcdFlashNvStorageFtwSpareSize."), FTWDxe refuses to initialize if
spare space base address or size is not aligned to block size.In EmuVariableFvbRuntimeDxe, FTW spare space base is set to a SubPtr inside the emulated NV storage, which is only guaranteed to align to 4KiB block. Make it align to EMU_FVB_BLOCK_SIZE to comply with the check. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Wei Liu <[email protected]> --- OvmfPkg/EmuVariableFvbRuntimeDxe/Fvb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/OvmfPkg/EmuVariableFvbRuntimeDxe/Fvb.c b/OvmfPkg/EmuVariableFvbRuntimeDxe/Fvb.c index c7c3fcb..d5b6721 100644 --- a/OvmfPkg/EmuVariableFvbRuntimeDxe/Fvb.c +++ b/OvmfPkg/EmuVariableFvbRuntimeDxe/Fvb.c @@ -867,7 +867,7 @@ FvbInitialize ( // // Initialize the Fault Tolerant Write spare block // - SubPtr = (VOID*) ((UINT8*) Ptr + EMU_FVB_BLOCK_SIZE); + SubPtr = (VOID*) (((UINTN) Ptr + EMU_FVB_BLOCK_SIZE) & ~(EMU_FVB_BLOCK_SIZE-1)); PcdSet32 (PcdFlashNvStorageFtwSpareBase, (UINT32)(UINTN) SubPtr); // -- 1.7.10.4 ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60134791&iu=/4140/ostg.clktrk _______________________________________________ edk2-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/edk2-devel
