ArmPkg/Include/Chipset: Fix translation table address calculations for AARCH64

TT_ADDRESS_* macros were not casting immediate values to UINTN.
This causes shift operations to be off by 32-bits when calculating
addresses above 4GB.  Any address above 4GB was being improperly calculated. 

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>

Index: ArmPkg/Include/Chipset/AArch64Mmu.h
===================================================================
--- ArmPkg/Include/Chipset/AArch64Mmu.h	(revision 14764)
+++ ArmPkg/Include/Chipset/AArch64Mmu.h	(working copy)
@@ -31,9 +31,9 @@
 
 // Return the smallest offset from the table level.
 // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
-#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel)  (12 + ((3 - (TableLevel)) * 9))
+#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel)  (UINTN)(12 + ((3 - (TableLevel)) * 9))
 
-#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level)     (1 << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
+#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level)     (UINTN)((UINTN)1 << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
 
 // Get the associated entry in the given Translation Table
 #define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address)  \
@@ -41,7 +41,7 @@
 
 // Return the smallest address granularity from the table level.
 // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
-#define TT_ADDRESS_AT_LEVEL(TableLevel)       (1 << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
+#define TT_ADDRESS_AT_LEVEL(TableLevel)       (UINTN)((UINTN)1 << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
 
 #define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \
     ((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))