In ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c:ArmConfigureMmu() there is a
section of code that puzzles me.
// Translate the Memory Attributes into Translation Table Register Attributes
if ((TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
(TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NON_CACHEABLE |
TCR_RGN_INNER_NON_CACHEABLE;
} else if ((TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
(TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
TCR |= TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WRITE_BACK_ALLOC |
TCR_RGN_INNER_WRITE_BACK_ALLOC;
} else if ((TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
(TranslationTableAttribute ==
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_WRITE_THROUGH |
TCR_RGN_INNER_WRITE_THROUGH;
} else {
// If we failed to find a mapping that contains the root translation table
then it probably means the translation table
// is not mapped in the given memory map.
ASSERT (0);
Status = RETURN_UNSUPPORTED;
goto FREE_TRANSLATION_TABLE;
}
The code will either adjust the TCR variable with the shareability bits [13:8]
or assert. The problem is that I don't see where the code following this does
anything with that adjusted value. Maybe I'm missing it, but I just don't see
it. Is it actually supposed to be written back into the TCR register, or is
just intended to get to the return of the unsupported?
Garrett Kirkendall [Description: Description: Description: purple]
SMTS Firmware Engineer | AMD Technology & Engineering
7171 Southwest Parkway, Austin, TX 78735 USA
[Description: Description: Description: image004]
facebook<https://www.facebook.com/AMD> | amd.com<http://www.amd.com/>
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