> On Jan 25, 2021, at 8:25 AM, Bill Frantz <[email protected]> wrote:
> 
> IEEE Binary Floating Point assumes (except in case of a very small, 
> de-normalized number), that the high order bit of the mantissa is a one. With 
> this assumption, it doesn't need to actually represent the one in memory. So, 
> it has 8 bits of exponent, 1 bit of sign, and 24 bits of mantissa crammed 
> into 32 bits. It should be able to handle the full precision of a 24 bit AtoD 
> converter.

If only we had 24 bits at RF. "Reasonable cost" for an ADC that can sample at 
120+ MHz gets you 16 bits at present.

Wayne
N6KR


> 
> 73 Bill AE6JV
> 
> On 1/25/21 at 8:15 AM, [email protected] (Bill Coleman) wrote:
> 
>> 
>>> On Jan 24, 2021, at 1:33 PM, Wayne Burdick <[email protected]> wrote:
>>> 
>>>> (Or did we have some other definition of “higher-performance”?)
>>> 
>>> Yes: More bits than 16, more monotonicity in the LSBs, general improvement 
>>> in SFDR, or lower
>> internal noise.
>>> 
>>> Adding more ADC bits does not require more DSP horsepower. The DSP is 32 
>>> bit floating point.
>> 
>> Well, that works up to 23-bits! (FP numbers have a 23-bit mantissa)
> 
> -----------------------------------------------------------------------
> Bill Frantz        | There's nothing so clear    | Periwinkle
> (408)348-7900      | as a design you haven't     | 150 Rivermead Rd #235
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