Does anyone have any experience with a test fixture for testing 40 DIP MOSIS chips for the AMI 0.5 um process that they'd like to share?
I'm looking to set something up. Since the 0.5 um process is 5V and most I/O on PCB today go up to 3.3V (although 5V tolerant), I'm wondering if there are any issues to be concerned about. Since 3.3V should be well above the VOH, things should still work although perhaps at a lower speed. I was thinking about using this neat looking logic analyzer/pattern generator (http://www.linkinstruments.com/lapatgen.htm) IO-3232A as the test fixture. I was also investigating FPGA (Altera DE2 board) and/ or an MBED (http://www.mbed.org) but it may be more trouble than its worth. If anyone would like to share details about their test setup, that would be most helpful. Thanks. Kind regards. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
